C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 319

• Manufacturer Part Number: C8051F966-A-GQ
• Description: 8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F966-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

To enable the Pulse Counter as a wake up source, enable the source in the PC0INT0/1 SFRs and enable
the Pulse Counter as a wake-up source by setting bit 0 (PC0WK) to 1 in the PMU0FL SFR. Upon waking,
firmware should read the PMCU0CF and PMU0FL SFRs to determine the wake-up source. If the PC0WK
bit is set indicating that the Pulse Counter has woke the MCU, firmware should read the flag bits
PC0INT0/1 SFRs to determine the Pulse Counter wake-up source and clear the flag bits before going back
to sleep.
PC0INT0 includes the more common interrupt and wake-up sources. These include comparator match,
counter overflow, and quadrature direction change. PC0INT1 includes interrupt and wake-up sources for
the advanced features, including flutter detection and quadrature error.
25.9. Real-Time Register Access
Several of the Pulse Counter registers values change in real-time synchronous to the RTC clock. Hard-
ware synchronization between the RTC clock domain and the system clock domain hardware would result
in long delays when reading real-time registers. Instead, real-time register values are available instanta-
neously, but the read must be qualified using the read valid bit (PC0TH bit 0). If the register value does not
change during the read access, the read valid bit will be set indicating the last was valid. If the value of the
real-time register changes during the read access, the read valid bit is 0, indicating the read was invalid.
After an invalid read, firmware must read the register and check the read valid bit again.
These 8-bit counter registers need to be qualified using the read valid bit:
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The 24-bit counters are three-byte real-time read-only registers that require a special access method for
reading. Firmware must read the low-byte (PC0CTR0L and PC0CTR1L) first and qualify using the read
valid bit. Reading the low-byte latches the middle and high bytes. If the read valid bit is 0, the read is invalid
and firmware must read the low-byte and check the read valid bit again. If the read valid bit is set, the read
is valid and the middle and high bytes are also safe to read. Firmware should read the middle and high
bytes only after reading the low byte and qualifying with the read valid bit.
The 24-bit compators are three-byte real-time read-write registers that require a special access method for
writing. Firmware must write the low-byte last. After writing the low-byte, it might take up to two RTC clock
cycles for the new comparator value to take effect. System designers should consider the synchronization
delay when setting the comparator value. The counter may be incremented before new comparator value
takes effect. Setting the comparator to at least 2 counts above the current count will eliminate the chance
of missing the comparator match during synchronization.
Example code is provided with accessor functions for all the real-time Pulse Counter registers.
25.10. Advanced Features
25.10.1. Quadrature Error
The quadrature encoder must only send valid quadrature codes. A valid quadrature sequence consists of
four valid states. The quadrature codes are only permitted to transition to one of the adjacent states, and
an invalid transition will result in a quadrature error. Note that a quadrature error is likely to occur when first
enabling the quadrature counter mode, since the Pulse Counter state machine starts at the LL state and
the initial state of the quadrature is arbitrary. It is safe to ignore the first quadrature error immediately after
initialization.
PC0STAT
PC0HIST
PC0INT0
PC0INT1
PC0CTR0L
PC0CTC1L
Rev. 0.5
C8051F96x
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