C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 285

• Manufacturer Part Number: C8051F966-A-GQ
• Description: 8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F966-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

SFR Definition 22.2. RSTSRC: Reset Source
SFR Page = 0x0; SFR Address = 0xEF.
Notes:
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
1. It is safe to use read-modify-write operations (ORL, ANL, etc.) to enable or disable specific interrupt sources.
2. If PORSF read back 1, the value read from all other bits in this register are indeterminate.
3. Writing a 1 to PORSF before the VDD Supply Monitor is stabilized may generate a system reset.
WDTRSF Watchdog Timer Reset Flag. N/A
MCDRSF Missing Clock Detector
FERROR Flash Error Reset Flag.
RTC0RE SmaRTClock Reset Enable
C0RSEF Comparator0 Reset Enable
PINRSF
SWRSF
PORSF
Name
RTC0RE
Varies
R/W
7
and Flag
and Flag.
Software Reset Force and
Flag.
(MCD) Enable and Flag.
Power-On / Power-Fail
Reset Flag, and Power-Fail
Reset Enable.
HW Pin Reset Flag.
FERROR
Varies
R
6
Description
C0RSEF
Varies
R/W
5
SWRSF
Varies
R/W
Rev. 0.5
0: Disable SmaRTClock
as a reset source.
1: Enable SmaRTClock as
a reset source.
N/A
0: Disable Comparator0 as
a reset source.
1: Enable Comparator0 as
a reset source.
Writing a 1 forces a sys-
tem reset.
0: Disable the MCD.
1: Enable the MCD.
The MCD triggers a reset
if a missing clock condition
is detected.
0: Disable the VDD Supply
Monitor as a reset source.
1: Enable the VDD Supply
Monitor as a reset
source.
N/A
4
3
WDTRSF
Varies
Write
R
3
MCDRSF
Varies
R/W
2
Set to 1 if SmaRTClock
alarm or oscillator fail
caused the last reset.
Set to 1 if Flash
read/write/erase error
caused the last reset.
Set to 1 if Comparator0
caused the last reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Set to 1 if Watchdog Timer
overflow caused the last
reset.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
Set to 1 anytime a power-
on or V
occurs.
Set to 1 if RST pin caused
the last reset.
C8051F96x
PORSF
Varies
R/W
DD
2
1
Read
monitor reset
PINRSF
Varies
R
0
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