C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 311

• Manufacturer Part Number: C8051F966-A-GQ
• Description: 8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F966-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

Internal Register Definition 24.10. ALARM1Bn: SmaRTClock Alarm 1 Match Value
SmaRTClock Address: ALARM1B0 = 0x0C; ALARM1B1 = 0x0D; ALARM1B2 = 0x0E; ALARM1B3 = 0x0F
Internal Register Definition 24.11. ALARM2Bn: SmaRTClock Alarm 2 Match Value
SmaRTClock Address: ALARM2B0 = 0x10; ALARM2B1 = 0x11; ALARM2B2 = 0x12; ALARM2B3 = 0x13
Note: The least significant bit of the alarm programmed value is iALARM1B0.0.
Note: The least significant bit of the alarm programmed value is ALARM2B0.0.
Name
Reset
Name
Reset
Type
Bit
7:0 ALARM1[31:0] SmaRTClock Alarm 1 Programmed Value.
Type
Bit
7:0 ALARM2[31:0] SmaRTClock Alarm 2 Programmed Value.
Bit
Bit
Name
Name
R/W
R/W
7
0
7
0
These 4 registers (ALARM1B3–ALARM1B0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should be disabled (ALRM1EN=0)
when updating these registers.
These 4 registers (ALARM2B3–ALARM2B0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should be disabled (ALRM2EN=0)
when updating these registers.
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
Rev. 0.5
ALARM1[31:0]
ALARM2[31:0]
4
0
4
0
Function
Function
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
C8051F96x
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
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