C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 278

• Manufacturer Part Number: C8051F966-A-GQ
• Description: 8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F966-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
22. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:




All SFRs are reset to the predefined values noted in the SFR descriptions. The contents of RAM are unaf-
fected during a reset; any previously stored data is preserved as long as power is not lost. Since the stack
pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal
oscillator. Refer to Section “23. Clocking Sources” on page 286 for information on selecting and configur-
ing the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its
clock source (Section “33.4. Watchdog Timer Mode” on page 477 details the use of the Watchdog Timer).
Program execution begins at location 0x0000.
278
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled
Px.x
Px.x
SmaRTClock
VBAT
System
Clock
Supply
Monitor
Comparator 0
+
-
RTC0RE
+
-
Enable
C0RSEF
Detector
Missing
Clock
(one-
shot)
DD
Microcontroller
EN
Extended Interrupt
Monitor and power-on resets, the RST pin is driven low until the device
CIP-51
Core
Handler
Figure 22.1. Reset Sources
WDT
PCA
EN
VDC
switch
VBAT
System Reset
Supply
Monitor
+
-
Rev. 0.5
Enable
(wired-OR)
(Software Reset)
SWRSF
Power Management
Block (PMU0)
'0'
Power On
VBAT
Reset
Illegal Flash
Reset
Operation
System Reset
Power-On Reset
Funnel
Reset
RST