MAX11200EEE+T Maxim Integrated, MAX11200EEE+T Datasheet - Page 8

• Manufacturer Part Number: MAX11200EEE+T
• Description: Analog to Digital Converters - ADC 24-Bit Delta-Sigma
• Manufacturer: Maxim Integrated

Specifications of MAX11200EEE+T

• Rohs: yes
• Number Of Channels: 1
• Architecture: Sigma-Delta
• Resolution: 24 bit
• Input Type: Single-Ended
• Interface Type: SPI
• Operating Supply Voltage: 1.7 V to 3.6 V, 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 3.6 V

MAX11200/MAX11210
24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
8
PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
RDY/DOUT
GPIO1
GPIO2
GPIO3
GPIO4
NAME
DVDD
AVDD
REFN
SCLK
REFP
AINN
AINP
GND
CLK
DIN
CS
General-Purpose I/O 1. Register controllable using SPI.
General-Purpose I/O 2. Register controllable using SPI.
General-Purpose I/O 3. Register controllable using SPI.
Ground. Ground reference for analog and digital circuitry.
Differential Reference Positive Input. REFP must be more positive than REFN. Connect REFP to a voltage
between AVDD and GND.
Differential Reference Negative Input. REFN must be more negative than REFP. Connect REFN to a
voltage between AVDD and GND.
Negative Fully Differential Analog Input
Positive Fully Differential Analog Input
Analog Supply Voltage. Connect a supply voltage between +2.7V and +3.6V with respect to GND.
Digital Supply Voltage. Connect a digital supply voltage between +1.7V and +3.6V with respect to GND.
Active-Low, Chip-Select Logic Input
Serial-Data Input. Data present at DIN is shifted to the device’s internal registers at the rising edge of
the serial clock at SCLK, when the device is accessed for an internal register write or for a command
operation.
Data Ready Output/Serial-Data Output. This output serves a dual function. In addition to the serial-data
output function, the RDY/DOUT also indicates that the data is ready when the RDY is logic-low. RDY/
DOUT changes on the falling edge of SCLK.
Serial-Clock Input. Apply an external serial clock to SCLK.
External Clock Signal Input. When external clock mode is selected (EXTCLK = 1), provide a 2.4576MHz
or 2.048MHz clock signal at CLK. Other frequencies can be used, but the data rate and digital filter notch
frequencies scale accordingly.
General-Purpose I/O 4. Register controllable using SPI.
TOP VIEW
GPIO1
GPIO2
GPIO3
REFN
REFP
AINN
AINP
GND
1
2
6
3
4
5
7
8
+
MAX11200
MAX11210
QSOP
FUNCTION
16
15
14
13
12
11
10
9
GPIO4
CLK
SCLK
RDY/DOUT
DIN
CS
DVDD
AVDD
Pin Configuration
Pin Description
Maxim Integrated