MAX11200EEE+T Maxim Integrated, MAX11200EEE+T Datasheet - Page 20

• Manufacturer Part Number: MAX11200EEE+T
• Description: Analog to Digital Converters - ADC 24-Bit Delta-Sigma
• Manufacturer: Maxim Integrated

Specifications of MAX11200EEE+T

• Rohs: yes
• Number Of Channels: 1
• Architecture: Sigma-Delta
• Resolution: 24 bit
• Input Type: Single-Ended
• Interface Type: SPI
• Operating Supply Voltage: 1.7 V to 3.6 V, 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 3.6 V

MAX11200/MAX11210
24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
The byte-wide CTRL2 register is a bidirectional read/write register. The byte written to the CTRL2 register controls the
direction and values of the digital I/O ports.
Table 13. CTRL2 Register (Read/Write)
DIR[4:1]: The direction bits configure the direction of the DIO bit. When a DIR bit is set to 0, the associated DIO bit
is configured as an input and the value returned by a read of the DIO bit is the value being driven on the associated
GPIO. When a DIR bit is set to 1, the associated DIO bit is configured as an output and the GPIO port is driven to a
logic value of the associated DIO bit.
DIO[4:1]: The data input/output bits are bits associated with the GPIO ports. When a DIO is configured as an input,
the value read from the DIO bit is the logic value being driven at the GPIO port. When the direction is configured as an
output, the GPIO port is driven to a logic value associated with the DIO bit.
The byte-wide CTRL3 register is a bidirectional read/write register. The CTRL3 register controls the operation and
calibration of the device.
Table 14. CTRL3 Register (Read/Write)
*These DGAIN_ bits are don’t-care bits for the MAX11200.
DGAIN[2:0] (MAX11210 Only): The digital gain bits control the input referred gain. With a gain of 1, the input range
is 0 to V
or ±V
to digital gains as follows:
NOSYSG: The no-system gain bit, NOSYSG, controls the system gain calibration coefficient. A 1 in this bit location
disables the use of the system gain value when computing the final offset and gain corrected data value. A 0 in this
location enables the use of the system gain value when computing the final offset and gain corrected data value.
NOSYSO: The no system offset bit, NOSYSO, controls the system offset calibration coefficient. A 1 in this location
disables the use of the system offset value when computing the final offset and gain corrected data value. A 0 in this
location enables the use of the system offset value when computing the final offset and gain corrected data value.
NOSCG: The no self-calibration gain bit, NOSCG, controls the self-calibration gain coefficient. A 1 in this location
disables the use of the self-calibration gain value when computing the final offset and gain corrected data value. A 0
in this location enables the use of the self-calibration gain value when computing the final offset and gain corrected
data value.
NOSCO: The no self-calibration offset bit, NOSCO, controls the use of the self-calibration offset coefficient. A 1 in this
location disables the use of the self-calibration offset value when computing the final offset and gain corrected data
value. A 0 in this location enables the use of the self-calibration offset value when computing the final offset and gain
corrected data value.
20
BIT
BIT NAME
DEFAULT
BIT
BIT NAME
DEFAULT
REF
REF
000 = 1
001 = 2
010 = 4
011 = 8
100 = 16
/gain. Digital gain is applied to the final offset and gain-calibrated digital data. The DGAIN[2:0] bits decode
(unipolar) or ±V
DGAIN2*
DIR4
B7
B7
0
0
REF
(bipolar). As the gain in increased by 2x, the input range is reduced to 0 to V
DGAIN1*
DIR3
B6
B6
0
0
DGAIN0*
DIR2
B5
B5
0
0
NOSYSG
DIR1
B4
B4
1
0
NOSYSO
DIO4
B3
B3
1
1
NOSCG
DIO3
B2
B2
1
1
CTRL2: Control 2 Register
CTRL3: Control 3 Register
NOSCO
DIO2
B1
B1
1
1
Maxim Integrated
RESERVED
REF
DIO1
B0
B0
1
0
/gain