MAX11200EEE+T Maxim Integrated, MAX11200EEE+T Datasheet - Page 11

• Manufacturer Part Number: MAX11200EEE+T
• Description: Analog to Digital Converters - ADC 24-Bit Delta-Sigma
• Manufacturer: Maxim Integrated

Specifications of MAX11200EEE+T

• Rohs: yes
• Number Of Channels: 1
• Architecture: Sigma-Delta
• Resolution: 24 bit
• Input Type: Single-Ended
• Interface Type: SPI
• Operating Supply Voltage: 1.7 V to 3.6 V, 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 3.6 V

Table 3a. Example of Self-Calibration
Table 3b. Example of System Calibration
The devices offer software-selectable internal oscillator
frequencies as well as software-selectable output data
rates. The LINEF bit in the CTRL1 register (Table 12)
determines the internal oscillator frequency. The RATE
bits in the command byte (Table 8) determine the ADC’s
output data rate. The devices also offer the option of
running in zero latency single-cycle conversion mode
(Table 2) or continuous conversion mode (Table 1). Set
SCYCLE = 0 in the CTRL1 register (Table 12) to run in
continuous conversion mode and SCYCLE = 1 for single-
cycle conversion mode.
Single-cycle conversion mode gives an output result with
no data latency. The devices output data up to 100sps
(2.048MHz internal oscillator) or 120sps (2.4576MHz
internal oscillator) with no data latency. In continuous
conversion mode, the output data rate is four times the
single-cycle conversion mode, for sample rates up to
400sps or 480sps. In continuous conversion mode, the
output data requires three additional 24-bit cycles to
settle from an input step.
Maxim Integrated
STEP
STEP
1
2
3
1
2
3
4
5
6
7
Initial power-up
Enable self-calibration registers
Self-calibration, DIN = 10010000
Initial power-up
Enable self-calibration registers
Self-calibration, DIN = 10010000
Enable system offset register
System-calibration offset, DIN = 1010000
Enable system gain register
System-calibration gain, DIN = 1011000
24-Bit, Single-Channel, Ultra-Low-Power,
DESCRIPTION
DESCRIPTION
Noise vs. Data Rate
Delta-Sigma ADCs with GPIO
0x000000
0x000000
0x00007E
0x000000
0x000000
0x00007E
0x00007E
0x00007E
0x00007E
0x00007E
SCOC
SCOC
0xBFD345
0xBFD345
0xBFD345
0xBFD345 0xFFEE1D
0xBFD345 0xFFEE1D
0xBFD345 0xFFEE1D 0x81CB5B
0x000000
0x000000
0x000000
0x000000
SCGC
SCGC
The devices include a SINC
spectral nulls at the multiples of the data rate. For all
data rates less than 30sps, a spectral null occurs at the
line frequency of 60Hz and is guaranteed to attenuate
60Hz normal-mode components by more than 100dB.
Simultaneous 50Hz and 60Hz attenuation can be accom-
plished by using an external clock with a frequency
of 2.25275MHz. This guarantees a minimum of 80dB
rejection at 50Hz and 85dB rejection at 60Hz. The SINC
filter has a -3dB frequency equal to 24% of the data rate.
See Figures 1 and 2.
The devices provide four GPIO ports. When set as out-
puts, these digital I/Os can be used to drive the digital
inputs to a multiplexer or multichannel switch. Figure 3
details an example where four single-ended signals are
multiplexed in a break-before-make switching sequence,
using the MAX313, a quad SPST analog switch.
The devices’ GPIO ports are configurable through the
CTRL2 register. See Table 13. To select AIN1, write the
command to CTRL2 according to Table 4a.
REGISTER
REGISTER
MAX11200/MAX11210
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
SOC
SOC
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
SGC
SGC
4
digital filter that produces
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
Digital Filter
BIT
BIT
1
0
0
1
0
0
0
0
0
0
GPIOs
1
0
0
1
0
0
0
0
0
0
11
4