MAX11200EEE+T Maxim Integrated, MAX11200EEE+T Datasheet - Page 14

• Manufacturer Part Number: MAX11200EEE+T
• Description: Analog to Digital Converters - ADC 24-Bit Delta-Sigma
• Manufacturer: Maxim Integrated

Specifications of MAX11200EEE+T

• Rohs: yes
• Number Of Channels: 1
• Architecture: Sigma-Delta
• Resolution: 24 bit
• Input Type: Single-Ended
• Interface Type: SPI
• Operating Supply Voltage: 1.7 V to 3.6 V, 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 3.6 V

MAX11200/MAX11210
24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
The MAX11200/MAX11210 interface is fully compatible
with SPI-, QSPI-, and MICROWIRE-standard serial inter-
faces. The SPI interface provides access to nine on-chip
registers that are 8 or 24 bits wide.
Drive CS low to transfer data in and out of the devices.
Clock in data at DIN on the rising edge of SCLK. The
RDY/DOUT output serves two functions: conversion sta-
tus and data read. To find the conversion status, assert
Figure 5. SPI Command Byte
14
Figure 6. SPI Register Access Write
Figure 7. SPI Register Access Read
RDY/DOUT
RDY/DOUT
HIGH-Z
HIGH-Z
SCLK
SCLK
DIN
DIN
CS
CS
RDY/DOUT
X
SCLK
t
CSH0
0
X
DIN
CS
t
CSS0
t
HIGH-Z
CSS0
t
DOE
1
1
t
t
1
1
DOE
CSH0
0
X
1
t
1
CSS0
t
DS
t
DS
Serial-Digital Interface
t
DOE
X
t
t
X
DH
DH
1
1
RS3
RS3
t
t
0
CL
CL
t
DS
t
CP
t
CP
RS2
RS2
t
CH
t
CH
CAL1
RS1
t
RS1
DH
RS0
RS0
CAL0
W/R
t
CL
8
W/R
t
CP
8
IMPD
t
t
DOT
CH
D7
CS low and read the RDY/DOUT output; the conversion
is in progress if the RDY/DOUT output reads logic-high
and the conversion is complete if the RDY/DOUT output
reads logic-low. Data at RDY/DOUT changes on the
falling edge of SCLK and is valid on the rising edge of
SCLK. DIN and DOUT are transferred MSB first. Drive
CS high to force DOUT high impedance and cause the
devices to ignore any signals on SCLK and DIN. Figures
5, 6, and 7 show the SPI timing diagrams.
9
D7
X
9
RATE2
D6
D6
X
t
DO1
D5
RATE1
D5
X
D4
D4
X
RATE0
t
DOH
D3
8
D3
t
X
CSH1
D2
D2
t
X
CSS1
D1
t
CSW
t
DOD
D1
X
D0
16
HIGH-Z
t
CSH1
Maxim Integrated
D0
X
16
t
DOD
t
CSS1
t
CSS1
t
CSW
t
DOD
HIGH-Z
HIGH-Z