MAX11200EEE+T Maxim Integrated, MAX11200EEE+T Datasheet - Page 4

• Manufacturer Part Number: MAX11200EEE+T
• Description: Analog to Digital Converters - ADC 24-Bit Delta-Sigma
• Manufacturer: Maxim Integrated

Specifications of MAX11200EEE+T

• Rohs: yes
• Number Of Channels: 1
• Architecture: Sigma-Delta
• Resolution: 24 bit
• Input Type: Single-Ended
• Interface Type: SPI
• Operating Supply Voltage: 1.7 V to 3.6 V, 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 3.6 V

MAX11200/MAX11210
24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
ELECTRICAL CHARACTERISTICS (continued)
(V
unless otherwise noted. Typical values are at T
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: V
Note 4: ppmFSR is parts per million of full scale.
Note 5: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
Note 6: For data rates (1, 2.5, 5, 10, 15)sps and (0.83, 2.08, 4.17, 8.33, 12.5)sps.
Note 7: Normal-mode rejection of power line frequencies of 60Hz/50Hz apply only for single-cycle data rates at 15sps/10sps and
4
POWER REQUIREMENTS
Analog Supply
Digital Supply
Total Operating Current
AVDD Sleep Current
AVDD Operating Current
DVDD Sleep Current
DVDD Operating Current
SPI TIMING CHARACTERISTICS
SCLK Frequency
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Low to 1st SCLK Rise Setup
CS High to 17th SCLK Setup
CS High After 16th SCLK Falling
Edge Hold
CS Pulse-Width High
DIN to SCLK Setup
DIN Hold After SCLK
RDY/DOUT Transition Valid After
SCLK Fall
RDY/DOUT Remains Valid After
SCLK Fall
RDY/DOUT Valid Before SCLK Rise
CS Rise to RDY/DOUT Disable
CS Fall to RDY/DOUT Valid
DATA Fetch
AVDD
= +3.6V, V
and bipolar input ranges.
lower or continuous data rate of 60sps/50sps.
AINP
PARAMETER
= V
AINN
DVDD
.
= +1.7V, V
REFP
SYMBOL
V
V
t
f
t
t
t
t
t
t
t
t
SCLK
CSH1
DVDD
CSS0
CSS1
AVDD
CSW
DOH
DOD
t
t
DOE
t
t
DOT
DOL
t
t
CH
DH
CP
CL
DS
DF
- V
REFN
A
AVDD + DVDD
Buffers disabled
Buffers enabled
60% duty cycle at 5MHz
Output transition time, data changes on
falling edge of SCLK
Output hold time allows for negative edge
data read
t
C
Default value of RDY is 1 for minimum
specification; maximum specification for
valid 0 on RDY/DOUT
Maximum time after RDY asserts to read
DATA register; t
conversion
= +25NC under normal conditions, unless otherwise noted.)
DOL
LOAD
= V
= t
AVDD
= 20pF
CL
- t
; internal clock, single-cycle mode (SCYCLE = 1), T
DOT
CONDITIONS
CNV
is the time for one
Buffers disabled
Buffers enabled
MIN
200
2.7
1.7
80
80
40
40
40
40
40
3
0
3
0
0
TYP
0.15
0.25
235
255
185
205
50
60 x t
A
t
MAX
CNV
300
235
Maxim Integrated
= T
3.6
3.6
65
40
25
40
2
2
5
CP
MIN
-
to T
UNITS
MHz
FA
FA
FA
FA
FA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
MAX
,