LP1072 FREESCALE [Freescale Semiconductor, Inc], LP1072 Datasheet - Page 6

• Manufacturer Part Number: LP1072
• Description: 802.11a/b/g Baseband System Solution
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Functional Description
3.1.8
TBA
3.1.9
TBA
3.1.10
This block contains all the control logic required to gate individual sub-block clocks.
3.2
3.2.1
The main function of the Protocol Accelerator Subsystem is to provide hardware acceleration functions
for the MAC Software to perform the time critical aspects of the 802.11 protocol.
The PAS contains the following:
3.2.2
The contents of the AES block are:
3.2.3
TBA
3.3
TBA
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Shared Memory Controller – provided arbitrated access to the shared memory (MAC memory)
WEP Hardware Engine
AES Hardware Engine
802.11 Protocol Accelerator – for support of time-critical MAC functions
Generic Host Interface
AES encryption/decryption core that performs AES encryption/decryption of a 128bit block.
Offset Codebook (OCB) mode encipher/decipher wrapper that performs OCB mode key
generation for the AES core.
DMA controller and Shared Memory Interface that controls the reading/writing of data blocks
from/to the PAS shared memory controller.
Control Registers, used to configure the operation of the AES block.
Media Access Control (MAC) Subsystem
PHY Subsystem
SDIO Registers
Clock Control
Clock Gating
Protocol Accelerator Subsystem (PAS)
AES Block
WEP Block
LP1072 Advance Information, Rev. 0.3
PRELIMINARY
Freescale Semiconductor