LP1072 FREESCALE [Freescale Semiconductor, Inc], LP1072 Datasheet - Page 16

• Manufacturer Part Number: LP1072
• Description: 802.11a/b/g Baseband System Solution
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Timers/Reset
5
The TCXO generates the 40MHz RFIC 800 mV clipped sine wave reference clock.
The TCXO output is converted to a digital signal via a clock squarer input pad circuit. The 40 MHz TCXO
reference is used to generate the 40 MHz IQDAC clock and the 20 MHz IQADC clock. The PLL
synthesizes a reference from the 40 MHz reference. The reference is then used to generate the BRC, ARM,
PAS and Symbol Processor clocks, the 44 MHz IQ DAC clock and the 22 MHz IQ ADC clock. When the
TCXO and PLL are powered down the only active clock source is the 32 kHz XTAL, a.k.a. the Slow Clock.
The TCXO, PLL and XTAL clock references all include bypass MUXes which allow the individual clock
reference to be driven by an external signal.
Figure 3
5.1
The LP1072 is clocked using an external crystal oscillator (XO) or a temperature compensated crystal
oscillator (TCXO) running at 40MHz with a frequency resolution of ± 20 ppm or better.
5.2
PLL Bypass
5.3
The LP1072 uses a low power 32 kHz crystal oscillator to maintain the timing during sleep.
16
Timers/Reset
illustrates the high level clocking of the LP1072 with the associated pins.
System Clock
PLL Block
Low Frequency Clock
TCXO_BYPASS_CLK
XTAL_BYPASS_CLK
PLL_BYPASS_CLK
XTAL_BYPASS
TCXO
XTAL
TCXO_BYPASS
PLL_BYPAS
FAST_CLK_PWR
S
32 kHz
40 MHz
Boundary
Chip
LP1072 Advance Information, Rev. 0.3
Figure 3. LP1072 Clocks
PLL
PRELIMINARY
Cuircuits
Control
Clock
88 MHz
44 MHz
40 MHz
20 MHz
22 MHz
32 kHz
ARM
AFE
Freescale Semiconductor