LP1072 FREESCALE [Freescale Semiconductor, Inc], LP1072 Datasheet - Page 12

• Manufacturer Part Number: LP1072
• Description: 802.11a/b/g Baseband System Solution
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

LP1072 Interfaces
12
Watchdog Status Register (offset 0x000E)
SDIO Host to Device Interrupt request register 0 (0x000F)
Device to SDIO Host Interrupt Source register 0 (0x0013)
Device to SDIO Host Interrupt Source register 1 (0x0014)
Bit
7:1
7:0
7:0
2:0
7:3
0
Wdog_reset
Reserved
Write_sdio_arm_int
Arm_to_sdio_int_clr[7:0] for
writes.
Arm_to_sdio_int_src[7:0] for
reads.
Arm_to_sdio_int_clr[10:8] for
writes.
Arm_to_sdio_int_src[10:8]
for reads.
Reserved
Name
This is a read only bit that when ‘1’ indicates that
the LP1072 ASIC has had a watchdog reset
occur.
Each bit in this register is 1 of 8 ARM interrupt
requests from the SDIO Host to the device ARM.
The Host should request an interrupt by writing a
“1” to the corresponding bit in this register. The
register will be read as a “1” until the ARM clears
the register. Once the ARM has cleared the
register then the corresponding bit will be read as
“0” again.
This register contains the interrupt pending status
of the SDIO Host interrupt from the device. The
device is capable of generating up to 8 individual
requests. Each bit in this register is ANDed with
the corresponding ARM to SDIO Host Interrupt
enable register. The ANDed bits are then ORed
together to generate a single SDIO Host interrupt
in the cccr register space. To clear a particular
interrupt bit the SDIO Host should write a “1” to
that particular bit in this register.
This register contains the interrupt pending status
of the SDIO Host semaphore 0-2 host granted
indication. When the Host requests a semaphore
the corresponding interrupt will be triggered when
the host has been granted the interrupt. Bit 0 is
semaphore 0; bit 1 is semaphore 1; and bit 2 is
semaphore 2. Each bit in this register is ANDed
with the corresponding ARM to SDIO Host
Interrupt enable register. The ANDed bits are then
ORed together to generate a single SDIO Host
interrupt in the cccr register space. To clear a
particular interrupt bit the SDIO Host should write
a “1” to that particular bit in this register.
Table 8. SDIO Function 1 Registers
LP1072 Advance Information, Rev. 0.3
PRELIMINARY
Description
—
—
Access
ARM
-⎯
-⎯
—
—
—
R
Freescale Semiconductor
Access
HOST
RW
RW
RW
-⎯
—
R
Reset
-⎯
0’s
0’s
0’s
—
0