LP1072 FREESCALE [Freescale Semiconductor, Inc], LP1072 Datasheet
LP1072
Related parts for LP1072
LP1072 Summary of contents
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... Document Number: LP1072 Rev. 0.3, 12/2005 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Functional Description . . . . . . . . . . . . . . . . . 4 4 LP1072 Interfaces . . . . . . . . . . . . . . . . . . . . . 10 5 Timers/Reset . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Pinout and Footprint . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . 24 8 Timing Characteristics . . . . . . . . . . . . . . . . . 26 9 Mechanical Dimensions . . . . . . . . . . . . . . . . 29 10 Development Support . . . . . . . . . . . . . . . . . 29 11 Appendix: Comparison of LP1071 and LP1072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 12 Revision History . . . . . . . . . . . . . . . . . . . . . 31 ...
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... The LP1072 was designed to target embedded devices and small form factor WLAN devices. Its support for SDIO and CompactFlash+ host interfaces combined with its ultra low power consumption and small size make it the optimal solution for mobile devices ...
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... C; < 95% humidity SDIO; compliant with SDIO Card Specifications, Version 1.00 CompactFlash+; compliant with CF+ and Compact Flash Specs Rev 2.0 16-bit SRAM emulation mode JTAG 8 GPIO pins One UART Serial EEPROM Microsoft Windows CE.net 3.0, 4.2 Microsoft Pocket PC 2002, 2003 LP1072 Advance Information, Rev. 0.3 PRELIMINARY Specifications 3 ...
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... Functional Description Feature Packaging Options Semiconductor Technology RF Support Certification 3 Functional Description Figure functional block diagram of the LP1072. On-Chip RAM/ROM ARM7TDMI Memory ARM Controller Subsystem Bridge Watchdog UART Timer Interrupt JTAG Controller EEPROM SDIO Interface Registers Clock GPIO Control RMB Clock ...
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... The LP1072 supports an external serial EEPROM for storing the boot loader, MAC address, calibration data and any other vendor-specific data. The LP1072 supports serial EEPROMs of sizes from 8 Kbit (organized as 1024 entries of 8 bits each, or 1024 512 Kbit (organized as 65,536 x 8). Serial EEPROMs from the following vendors have been tested and verified to work with the LP1072: • ...
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... DMA controller and Shared Memory Interface that controls the reading/writing of data blocks from/to the PAS shared memory controller. • Control Registers, used to configure the operation of the AES block. 3.2.3 WEP Block TBA 3.3 PHY Subsystem TBA 6 LP1072 Advance Information, Rev. 0.3 PRELIMINARY Freescale Semiconductor ...
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... Fixed capacitance Switched capacitance @Fs — — — Fin= 1MHz Fin= 10MHz Fin= 1MHz Fin= 10MHz Fin= 1MHz Fin= 10MHz Gain Phase — LP1072 Advance Information, Rev. 0.3 PRELIMINARY Functional Description Resolution Clock 8-bit 22 Msps 8-bit 44 Msps 6-bit 10 Msps 8-bit 1 Msps 8-bit 20 Msps ...
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... Fin= 1MHz Fin= 10MHz Fin= 1MHz Fin= 10MHz Fin= 1MHz Fin= 10MHz Gain Phase — From Shutdown From Standby LP1072 Advance Information, Rev. 0.3 PRELIMINARY Min Typ Max — — 1 — — 10 Min Typ Max — 8 — ...
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... Fin= 100 kHz Table 6. Table 6. Aux ADC Specifications Condition Min — — — — — — Fin= 100 kHz Gain Phase From Shutdown From Standby LP1072 Advance Information, Rev. 0.3 PRELIMINARY Functional Description Typ Max — 6 — 10 — — 6 — 3 — ...
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... Due to saturation of the output buffer, INL and DNL are not applicable for output voltages below 200 mV. Output is monotonic above 0 LP1072 Interfaces 4.1 SDIO Host Interface The LP1072 supports SDIO Card Specifications, Version 1.00 (http//www.sdcard.org). The LP1072 SDIO host interface supports the I/O mode of the SD Card Specifications. 4.1.1 SDIO Supported Features The features supported by the LP1072 SDIO host interface are: • ...
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... SDIO Mailbox semaphore 1 0x001E SDIO Mailbox semaphore 2 0x0020 Reserved 0x1FFF 2 KByte Mailbox 0x2000 space 0x27FF 0x2800 Reserved 0x3FFF 0x4000 8Kbyte Internal Memory 0x5FFF LP1072 Advance Information, Rev. 0.3 PRELIMINARY LP1072 Interfaces illustrates SDIO Function 1 0x200E RAM0 0x200F RAM1 0x23FF RAM2 0x2400 11 ...
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... Table 8. SDIO Function 1 Registers Description This is a read only bit that when ‘1’ indicates that the LP1072 ASIC has had a watchdog reset occur. — Each bit in this register ARM interrupt requests from the SDIO Host to the device ARM. ...
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... If the value read is “11” then the device owns access to the mailbox. When the host is done utilizing the mailbox then it should release ownership of the mailbox by writing “00” to this register. -⎯ LP1072 Advance Information, Rev. 0.3 PRELIMINARY LP1072 Interfaces ARM HOST Reset ...
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... If the Host has not been granted access to the mailbox it will not be able to read or write the mailbox. Once the Host is finished with the mailbox it should release control of the mailbox as described in the mailbox semaphore 2 register. LP1072 Advance Information, Rev. 0.3 PRELIMINARY ARM HOST Reset ...
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... CompactFlash+ Host Interface The LP1072 supports CF+ and Compact Flash Specification Revision 2.0. The LP1072 CF host interface supports both the I/O and storage modes of the Compact Flash Specifications. The interface allows an external host (or an host DMA) to have 8-bit or 16-bit memory and I/O mode access to the device according to the Compact Flash Specification 2 ...
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... The LP1072 is clocked using an external crystal oscillator (XO temperature compensated crystal oscillator (TCXO) running at 40MHz with a frequency resolution of ± 20 ppm or better. 5.2 PLL Block PLL Bypass 5.3 Low Frequency Clock The LP1072 uses a low power 32 kHz crystal oscillator to maintain the timing during sleep. 16 Clock Control Cuircuits PLL Figure 3. LP1072 Clocks LP1072 Advance Information, Rev ...
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... Core ground pad (25mA per pad max current) Input ARM7TDMI Icebreaker debug enable pin Input Embedded board reset Input Bypass the internal PLL and use PLL_BYPASS_CLK Input PLL bypass clock input LP1072 Advance Information, Rev. 0.3 PRELIMINARY Pinout and Footprint Description Pin N11 ...
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... Bi-dir General Purpose I/O Bi-dir General Purpose I/O Bi-dir General Purpose I/O Bi-dir General Purpose I/O Input UART input data Output UART output data Bi-dir General Purpose I/O dedicated for EEPROM LP1072 Advance Information, Rev. 0.3 PRELIMINARY Description Freescale Semiconductor Pin C11 D11 D15 D13 ...
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... Chip Enable odd address (8 bit mode) Bi-dir CompactFlash address Bi-dir CompactFlash address Bi-dir CompactFlash address Bi-dir CompactFlash address Bi-dir CompactFlash address Bi-dir CompactFlash address Bi-dir CompactFlash address Bi-dir CompactFlash address LP1072 Advance Information, Rev. 0.3 PRELIMINARY Pinout and Footprint Description Pin ...
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... ADC Negative reference for decoupling Input ADC Positive reference for decoupling Input Muxed analog input to auxiliary ADC bit 0 Input Muxed analog input to auxiliary ADC bit 1 Input Muxed analog input to auxiliary ADC bit 2 LP1072 Advance Information, Rev. 0.3 PRELIMINARY Description Freescale Semiconductor Pin P9 P10 R13 N12 ...
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... RF VGA setting. Driven by UWA. Output RF VGA setting. Driven by UWA. Output RF VGA setting. Driven by UWA. Output RF Rx highpass filter setting. Driven by UWA. Output RF antenna select. Driven by ARM. Output RF antenna select. Driven by ARM. LP1072 Advance Information, Rev. 0.3 PRELIMINARY Pinout and Footprint Description Pin ...
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... Table 9. Pin Description (continued) Direction Output RF 3-wire serial interface. Driven by ARM. Output RF 3-wire serial interface. Driven by ARM. Output RF 3-wire serial interface. Driven by ARM. Input RF lock detect. Read by ARM. LP1072 Advance Information, Rev. 0.3 PRELIMINARY Description Freescale Semiconductor Pin G12 H14 G15 G14 ...
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... ARM_ ARM_ CF_A_7 UART EEPROM _0_DI _CLK_ GPIO ARM_ CF_A_5 JTAG_ CF_A_8 UART RESET _6 _0_DO CF_A_3 CF_A_4 VDD_ CF_A_6 CORE_2 LP1072 Advance Information, Rev. 0.3 PRELIMINARY Pinout and Footprint QDACOUTN PLL_ RE- _1 BYPASS SERVED _CLK RE- NC SERVED FAST_CLK TCXO_ NC _POWER ...
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... Storage Temperature Electrostatic Discharge Voltage Operating the LP1072 under conditions that exceed Absolute Maximum Ratings may result in permanent damage to the device. Absolute maximum ratings are limiting values, and are considered individually, while all other parameters are within their specified operating ranges. ...
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... 2,4,…, 24mA =2,4,…, 24mA LP1072 Advance Information, Rev. 0.3 PRELIMINARY DC Electrical Specifications Min Typ Max Units 1.62 1.8 1.98 3.0 3.3 3.6 -0.3 — 0.8 2.0 — 5.5 1.46 1.58 1.75 1.47 1.50 1.50 0.90 0.94 0.96 -10 — 10 -10 — ...
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... Timing Characteristics 8 Timing Characteristics 8.1 AFE Interface 8.1.1 I/Q ADC Figure 4. Timing of the Pipelining Operation in I/Q ADC 8.1.2 I/Q DAC Figure 5. Timing Diagram of the I/Q DAC Inputs and Outputs 26 LP1072 Advance Information, Rev. 0.3 PRELIMINARY Freescale Semiconductor ...
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... RSSI ADC Figure 6. Timing of the RSSI ADC Pipelining Operation Figure 7. Timing of the Aux ADC Successive Approximation Operation Freescale Semiconductor LP1072 Advance Information, Rev. 0.3 PRELIMINARY Timing Characteristics 27 ...
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... Timing Characteristics 8.1.4 Auxiliary DAC Figure 8. Conversion Cycle in Normal Operation for Aux DAC Symbol Parameter tpd Propagation delay ts Settling time 28 Table 14. Aux DAC Timing Parameters Min Typ — 5 — 80 LP1072 Advance Information, Rev. 0.3 PRELIMINARY Max Units — ns — ns Freescale Semiconductor ...
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... Mechanical Dimensions The LP1072 is a 200-pin Very-thin Fine-pitch Ball Grid Array (VFBGA) package. All dimensions are mm. 10 Development Support In addition to the LP1072 baseband and MAC, Freescale provides developers with reference designs, development platform, software drivers, system development software, testing and debugging tools and a full set of technical documentation that includes: • ...
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... Appendix: Comparison of LP1071 and LP1072 11 Appendix: Comparison of LP1071 and LP1072 Table 15. Comparison of LP1071 and LP1072 Item Network Standard Support Network Architectures Data Rates Modulation Techniques Security 1 Receiver Sensitivity Power Consumption Supply Voltage Operating Temperature Host Interface Other Interfaces Operating System Support ...
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... Revision History This document’s updated format reflects that Freescale Semiconductor, Inc. acquired CommASIC on October 20, 2005. Since the release of the previous version of this document (Rev. 0.2), the technical content has not been updated. Freescale Semiconductor LP1072 Advance Information, Rev. 0.3 PRELIMINARY Revision History 31 ...
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... P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: LP1072 Rev. 0.3 12/2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...