K4T51043QG SAMSUNG [Samsung semiconductor], K4T51043QG Datasheet - Page 27

• Manufacturer Part Number: K4T51043QG
• Description: 512Mb G-die DDR2 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4T51043QG
K4T51083QG
K4T51163QG
Table 3 - DDR2-400/533 tDS1/tDH1 derating with single-ended data strobe
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the
∆tDS and ∆tDH derating value respectively. Example: tDS (total setup time) =tDS(base) +∆tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V
If the actual signal is always earlier than the nominal slew rate line between shaded ’V
(See Figure 5 for differential data strobe and Figure 6 for single-ended data strobe.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ’V
Figure 7 for differential data strobe and Figure 8 for single-ended data strobe)
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V
the actual signal is always later than the nominal slew rate line between shaded ’dc level to V
(see Figure 9 for differential data strobe and Figure 10 for single-ended data strobe) If the actual signal is earlier than the nominal slew rate line anywhere
between shaded ’dc to V
(see Figure 11 for differential data strobe and Figure 12 for single-ended data strobe)
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V
transition) a valid input signal is still required to complete the transition and reach V
For slew rates in between the values listed in Tables 1, 2 and 3, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Slew
V/ns
rate
DQ
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
∆tDS
188
146
63
1
2.0 V/ns
-
-
-
-
-
-
∆tDS1, ∆tDH1 Derating Values for DDR2-400, DDR2-533(All units in ‘ps’; the note applies to the entire table)
REF
(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see
∆tDH
188
167
125
REF
1
-
-
-
-
-
-
(DC) region’, the slew rate of a tangent line to the actual signal from the dc level to V
∆tDS
167
125
42
31
1
1.5 V/ns
-
-
-
-
-
∆tDH
146
125
83
69
1
-
-
-
-
-
∆tDS
125
-11
-25
83
1
0
1.0 V/ns
-
-
-
-
∆tDH
-14
-31
63
42
1
0
-
-
-
-
∆tDS
-13
-27
-45
81
-2
1
0.9 V/ns
-
-
-
-
DQS Single-ended Slew Rate
∆tDH
-13
-30
-53
43
1
1
-
-
-
-
27 of 47
∆tDS
-18
-32
-50
-74
-7
1
0.8 V/ns
-
-
-
-
IH/IL
∆tDH
-13
-27
-44
-67
-96
(AC).
1
-
-
-
-
REF
(DC) to ac region’, use nominal slew rate for derating value
∆tDS
-128
-29
-43
-61
-85
1
REF
0.7 V/ns
-
-
-
-
(DC) region’, use nominal slew rate for derating value
∆tDH
-114
-156
-45
-62
-85
1
-
-
-
-
IH
IL
REF
REF
(DC)min and the first crossing of V
(DC)max and the first crossing of V
∆tDS
-102
-145
-210
-60
-78
1
0.6 V/ns
-
-
-
-
(DC) and the first crossing of V
(DC) and the first crossing of V
REF
Rev. 1.4 December 2008
IH/IL
∆tDH
-109
-138
-180
-243
-86
(DC) level is used for derating value
1
-
-
-
-
(AC) at the time of the rising clock
DDR2 SDRAM
∆tDS
-108
-138
-175
-240
1
0.5 V/ns
-
-
-
-
-
∆tDH
-152
-181
-223
-286
1
-
-
-
-
-
∆tDS
-183
-226
-291
1
0.4 V/ns
-
-
-
-
-
-
IL
REF
IH
(AC)max.
(AC)min.
REF
(DC). If
∆tDH
-246
-288
-351
(DC).
1
-
-
-
-
-
-