K4T51043QG SAMSUNG [Samsung semiconductor], K4T51043QG Datasheet - Page 24

• Manufacturer Part Number: K4T51043QG
• Description: 512Mb G-die DDR2 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4T51043QG
K4T51083QG
K4T51163QG
14.0 General notes, which may apply for all AC parameters
1. DDR2 SDRAM AC timing reference load
Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise repre
sentation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other
simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally
a coaxial transmission line terminated at the tester electronics).
2. Slew Rate Measurement Levels
a) Output slew rate for falling and rising edges is measured between V
b) Input slew rate for single ended signals is measured from V
c) V
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in Figure 2.
signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
The output timing reference voltage level for single ended signals is the crosspoint with V
(e.g. DQS - DQS) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by
design, but is not necessarily tested on each device.
edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = + 500 mV (+ 250 mV to -
500 mV for falling edges).
ID
is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe.
V
DUT
DDQ
V
DDQ
RDQS, RDQS
DUT
DQS, DQS
Figure 2 - Slew Rate Test Load
RDQS
RDQS
DQ
DQS
DQS
DQ
Output
Figure 1 - AC Timing Reference Load
Output
REF
Test point
Timing
reference
point
(DC) to V
TT
24 of 47
- 250 mV and V
IH(
AC),min for rising edges and from V
25
Ω
25
Ω
TT
TT
+ 250 mV for single ended signals. For differential signals
. The output timing reference voltage level for differential
V
TT
V
= V
TT
= V
DDQ
DDQ
/2
/2
Rev. 1.4 December 2008
REF
(DC) to V
DDR2 SDRAM
IL
(AC),max for falling