ZL50011/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50011/GDC Datasheet - Page 58

• Manufacturer Part Number: ZL50011/GDC
• Description: Flexible 512 Channel DX with on-chip DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note: # denotes input stream from 0 to 7
15 - 10
External Read/Write Address: 101
Reset Value: 0000
9 - 3
2 - 0
Bit
SIDR0
SIDR1
SIDR2
SIDR3
SIDR4
SIDR5
SIDR6
SIDR7
STIN#CD6 - 0
STIN#BD2 - 0
15
0
0
0
0
0
0
0
0
Unused
Name
14
0
0
0
0
0
0
0
0
H
Table 26 - Stream Input Delay Register 0 to 7 (SIDR0 to SIDR7)
13
0
0
0
0
0
0
0
0
Reserved. In normal functional mode, these bits MUST be set to zero.
Input Stream# Channel Delay Bits:
The binary value of these bits refers to the number of channels that the input
stream will be delayed. This value should not exceed the maximum channel
number of the stream. Zero means no delay.
Input Stream# Bit Delay Bits:
The binary value of these bits refers to the number of bits that the input stream
will be delayed. This maximum value is 7. Zero means no delay.
12
0
0
0
0
0
0
0
0
H
11
,
0
0
0
0
0
0
0
0
103
10
0
0
0
0
0
0
0
0
Zarlink Semiconductor Inc.
H
,
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
CD6
CD6
CD6
CD6
CD6
CD6
CD6
CD6
ZL50011
9
105
H
58
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
CD5
CD5
CD5
CD5
CD5
CD5
CD5
CD5
,
8
107
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
CD4
CD4
CD4
CD4
CD4
CD4
CD4
CD4
7
H
,
Description
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
CD3
CD3
CD3
CD3
CD3
CD3
CD3
CD3
6
109
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
H
CD2
CD2
CD2
CD2
CD2
CD2
CD2
CD2
5
,
10B
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
CD1
CD1
CD1
CD1
CD1
CD1
CD1
CD1
4
H
,
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
CD0
CD0
CD0
CD0
CD0
CD0
CD0
CD0
3
10D
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
BD2
BD2
BD2
BD2
BD2
BD2
BD2
BD2
H
2
,
10F
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
BD1
BD1
BD1
BD1
BD1
BD1
BD1
BD1
1
Data Sheet
H
,
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
BD0
BD0
BD0
BD0
BD0
BD0
BD0
BD0
0