ZL50011/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50011/GDC Datasheet - Page 47

• Manufacturer Part Number: ZL50011/GDC
• Description: Flexible 512 Channel DX with on-chip DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

7.0
12 - 10
External Read/Write Address: 000
Reset Value: 0000
Bit
MODE
15
14
13
9
8
7
FBD
15
Detail Register Description
SLV
14
CKIN2-0
FBDEN
CKFP2
CKFP1
CKFP0
MODE
Name
FBD-
SLV
FBD
EN
13
H
CKIN
Frame Boundary Determination Mode Select.
When either the FBDEN or FBDMODE bit is set low, the frame boundary discriminator
(FBD) is disabled.
When both the FBDEN and FBDMODE bits are set HIGH, the frame discriminator (FBD)
is enabled. The device will have 20 ns of input clcok jitter tolerance (on CKi and FPi)
when the FBD is enabled.
By default, the FBDEN and FBDMODE bits are Low. Both the FBDEN and FBDMODE
bits should be set HIGH during normal operation.
DPLL Bypass Mode Enable.
When this bit is zero, the DPLL is in Master or Freerun mode. When this bit is high, the
DPLL is in Bypass mode.
Frame Boundary Determinator Enable.
When either the FBDEN or FBDMODE bit is set low, the frame boundary discriminator
(FBD) is disabled.
When both the FBDEN and FBDMODE bits are set HIGH, the frame discriminator (FBD)
is enabled. The device will have 20ns of input clcok jitter tolerance (on CKi and FPi)
when the FBD is enabled.
By default, the FBDEN and FBDMODE bits are Low. Both the FBDEN and FBDMODE
bits should be set HIGH during normal operation.
Input ST Bus Clock (CKi) and Frame Pulse (FPi) Selection.
Output ST Bus clock CKo2 and frame pulse FPo2 Selection.
When this bit is low, CKo2 is 32.768 MHz clock and FPo2 is 30 ns wide frame pulse
When this bit is high, CKo2 is 16.384 MHz clock and FPo2 is 61 ns wide frame pulse
Output ST Bus clock CKo1 and frame pulse FPo1 Selection.
When this bit is low, CKo1 is 16.384 MHz clock and FPo1 is 61 ns wide frame pulse
When this bit is high, CKo1 is 8.192 MHz clock and FPo1 is 122 ns wide frame pulse
Output ST Bus clock CKo0 and frame pulse FPo0 Selection.
When this bit is low, CKo0 is 4.096 MHz clock and FPo0 is 244 ns wide frame pulse
When this bit is high, CKo0 is 8.192 MHz clock and FPo0 is 122 ns wide frame pulse
12
2
CKIN
11
1
Table 16 - Control Register (CR) Bits
H
CKIN
10
0
CKIN2 - 0
011 - 111
CKFP
000
001
010
9
2
Zarlink Semiconductor Inc.
ZL50011
CKFP
8
1
47
CKFP
FPi Low Cycle
7
0
Description
122 ns
244 ns
61 ns
CBER
6
Reserved
SBER
5
MBPE
4
16.384 MHz
8.192 MHz
4.096 MHz
OSB
CKi
3
MS2
2
Data Sheet
MS1
1
MS0
0