ZL50011/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50011/GDC Datasheet - Page 54

• Manufacturer Part Number: ZL50011/GDC
• Description: Flexible 512 Channel DX with on-chip DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

15 - 9
External Read/Write Address: 100
Reset Value: 0000
Bit
SICR0
SICR1
SICR2
SICR3
SICR4
SICR5
SICR6
SICR7
8
7
6
5
15
0
0
0
0
0
0
0
0
STIN#QEN3
STIN#QEN2
STIN#QEN1
STIN#QEN0
Unused
Name
14
0
0
0
0
0
0
0
0
Table 24 - Stream Input Control Register 0 to 7 (SICR0 to SICR7)
H
13
0
0
0
0
0
0
0
0
12
0
0
0
0
0
0
0
0
Reserved. In normal functional mode, these bits MUST be set to zero.
Quadrant Frame 3 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch24 to
31, Ch48 to 63 and Ch96 to 127 for the 2.048 Mbps, 4.096 Mbps and
8.192 Mbps mode respectively.
Quadrant Frame 2 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch16 to
23, Ch32 to 47 and Ch64 to 95 for the 2.048 Mbps, 4.096 Mbps and
8.192 Mbps mode respectively.
Quadrant Frame 1 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch8 to 15,
Ch16 to 31 and Ch32 to 63 for the 2.048 Mbps, 4.096 Mbps and 8.192 Mbps
mode respectively.
Quadrant Frame 0 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch0 to 7,
Ch0 to 15 and Ch0 to 31 for 2.048 Mbps, the 4.096 Mbps and 8.192 Mbps
mode respectively.
H
11
0
0
0
0
0
0
0
0
,
102
10
0
0
0
0
0
0
0
0
Zarlink Semiconductor Inc.
H
,
ZL50011
9
104
0
0
0
0
0
0
0
0
H
54
,
STIN0
QEN3
STIN1
QEN3
STIN2
QEN3
STIN3
QEN3
STIN4
QEN3
STIN5
QEN3
STIN6
QEN3
STIN7
8
106
STIN0
QEN2
STIN1
QEN2
STIN2
QEN2
STIN3
QEN2
STIN4
QEN2
STIN5
QEN2
STIN6
QEN2
STIN7
7
H
,
Description
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
QEN1
QEN1
QEN1
QEN1
QEN1
QEN1
QEN1
108
6
H
,
STIN0
QEN0
STIN1
QEN0
STIN2
QEN0
STIN3
QEN0
STIN4
QEN0
STIN5
QEN0
STIN6
QEN0
STIN7
5
10A
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
SMP1
SMP1
SMP1
SMP1
SMP1
SMP1
SMP1
4
H
,
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
SMP0
SMP0
SMP0
SMP0
SMP0
SMP0
SMP0
10C
3
H
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
,
DR2
DR2
DR2
DR2
DR2
DR2
DR2
2
10E
Data Sheet
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
DR1
DR1
DR1
DR1
DR1
DR1
DR1
1
H
,
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
DR0
DR0
DR0
DR0
DR0
DR0
DR0
0