ZL50011/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50011/GDC Datasheet - Page 26

• Manufacturer Part Number: ZL50011/GDC
• Description: Flexible 512 Channel DX with on-chip DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL50011
Data Sheet
2.3.7
External High Impedance Control, STOHZ 0 to 15
The STOHZ 0 to 15 outputs are provided to control the external tristate ST-BUS drivers for per-channel high
impedance operations. The STOHZ outputs are sent out in 32, 64 or 128 timeslots corresponding to the output
channels for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps output streams respectively. Each control timeslot lasts for
one channel time.
When the ODE pin is high, the STOHZ 0 - 15 are enabled. When the ODE pin or the RESET pin is low, the STOHZ
0 - 15 are driven high. STOHZ outputs are also driven high if their corresponding ST-BUS outputs are not in use.
Figure 20 gives an example when channel 2 of a given ST-BUS output is programmed in the high impedance state,
the corresponding STOHZ pin drives high for one channel time at the channel 2 timeslot.
By default, the output timing of the STOHZ signals follow the same timing as their corresponding STo signals
including any user-programmed output channel and bit delay and fractional bit advancement. In addition, the device
allows users to advance the STOHZ signals from their default positions to a maximum of four 15.2 ns steps (or four
1/4 bit steps) using Bit 3 to 5 of the Stream Output Control Register (SOCR). Bit 6 in the Stream Output Control
Register selects the step resolution as 15.2 ns or 1/4 data bit. The additional advancement feature allows the
STOHZ signals to better match the high impedance timing required by the external ST-BUS drivers.
When the device is in DPLL Master mode (or Freerun mode) and the additional STOHZ advancement is set to zero,
there is no phase difference between the STo0 - 15 and the STOHZ 0 to 15. When the device is in DPLL Master
mode (or Freerun mode) and the additional STOHZ advance is not zero, the phase correction of 6.25 ns could
happen between the STo0 - 15 and STOHZ 0 to 15 because these outputs are clocked by various internal clock
edges and the DPLL output has the intrinsic jitter of 6.25 ns.
When the device is in the DPLL Bypass Mode, there is no phase correction between the STo0 -15 of the STOHZ 0
- 15 regardless whether the additional STOHZ advancement is enabled or disabled.
FPo
HiZ
Ch0
SToY
Last Ch
Ch0
Ch1
Ch2
Ch3
Last Ch -2
Last Ch-1
Last Ch
STOHZ Y
(Default = No Adv.)
STOHZ Advancement (Programmable in 4 steps of 15.2 ns or 1/4 bit)
STOHZ Y
(With Adv.)
Note: Y = 0 to 15
Output Frame Boundary
Note: Last Channel = 31, 63, 127 for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps mode respectively
Figure 20 - Example: External High Impedance Control Timing
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Zarlink Semiconductor Inc.