ZL50011/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50011/GDC Datasheet - Page 18

• Manufacturer Part Number: ZL50011/GDC
• Description: Flexible 512 Channel DX with on-chip DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.1.3
When the negative input frame pulse and negative input clock formats are used, the input frame boundary is
defined by the falling edge of the CKi input clock while the FPi is low. When the input data rate is 2.048 Mbps,
4.096 Mbps or 8.192 Mbps, there are 32, 64 or 128 channels per every ST-BUS frame respectively. Figure 7 shows
the details:
2.1.4
The ZL50011 has a Frame Boundary Determinator (FBD) allowing substantial increase of the CKi input clock jitter
tolerance. The FBD circuit is enabled by setting the Control Register bits FBDEN and FBDMODE to HIGH. By
default the FBD is disabled. Both the FBDEN and FBDMODE bits should be set HIGH during normal operation. The
device can have 20 ns of input clock jitter tolerance (on CKi and FPi) when the FBD is fully enabled.
This jitter tolerance is related to the proper operation of the switch, and describes the amount of jitter that can be
accepted on the CKi and FPi inputs. Do not confuse this with the DPLL jitter tolerance (Section 2.11.2) which
describes the ability of the integrated DPLL to lock to an input reference (REF).
(16.384 MHz)
(2.048 Mbps)
(4.096 Mbps)
(8.192 Mbps)
(4.096 MHz)
(8.192 MHz)
Input Frame Boundary
ST-BUS Input Timing
Improved Input Jitter Tolerance with Frame Boundary Determinator
(8kHz)
CKi
CKi
CKi
FPi
FPi
STi
FPi
STi
STi
3
1
2
0
1 0
Figure 7 - ST-BUS Input Timing for Various Input Data Rates
0
7
7
6
7
5
Channel 0
6
4
3
5
2
6
Channel 0
1 0
4
7
Zarlink Semiconductor Inc.
3
6
5
5
Channel 0
Channel 1
ZL50011
2
4
3
1
18
2
4
1 0
0
6
3
5
Channel 126
6
4
Channel 31
3
5
2
Input Frame Boundary
2
Channel 63
1 0
4
7
3
6
1
5
Channel 127
2
4
3
1
2
0
1 0
0
Data Sheet
7 6
7
7