ZL50011/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50011/GDC Datasheet - Page 33

• Manufacturer Part Number: ZL50011/GDC
• Description: Flexible 512 Channel DX with on-chip DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Table 14 shows the three operating modes of the DPLL. The DPLL is controlled by the DOM (DPLL Operation
Mode) register and bit 14 of the Control Register (CR). The DPLL’s status is reported in the DPLL House Keeping
Register (DHKR). The DPOA (DPLL Output Adjustment) register advances or delays the ST-BUS outputs with
respect to the reference. These registers are described in Table 16 on page 47 for CR, Table 21 on page 52 for
DOM, Table 22 on page 53 for DOA, and Table 23 on page 53 for DHKR.
The DPLL intrinsic jitter is 6.25 ns peak to peak. In Master and Freerun modes, the DPLL intrinsic jitter will be
added onto the ST-BUS outputs. In Bypass mode, the DPLL is completely bypassed and the DPLL intrinsic jitter will
not be added to the ST-BUS outputs.
2.9.1
DPLL Master mode is selected by the setting shown in Table 14. Asserting the RESET pin low will also put the
DPLL into Master mode since RESET clears all the registers. In Master mode, the DPLL generates the MCKTDM
clock synchronized to the timing reference and provides jitter attenuation. MCKTDM provides timing for the TDM
switching function and for the ST-BUS outputs. Hence the Master mode ST-BUS output clocks and frame pulses
are synchronized to the reference and can be used to provide a system’s ST-BUS timing.
The DPLL has access to an independent external reference at the REF input pin. Typically REF is from the
network. Alternatively, REF can be replaced by an internal 8 kHz signal (CKi/FPi) derived from the CKi and FPi
inputs.
The nominal frequency of the REF input can be programmed to be either 8 kHz, 1.544 MHz or 2.408 MHz via the
FP1-0 bits of the DOM register. When the internal 8 kHz signal CKi/FPi is selected as the reference instead of REF,
the FP1-0 bits must be set to 00.
The DPLL operates on the rising edge of the selected reference. The polarity of the REF input can be inverted via
the PINV bit of the DOM register.
The selected reference (either REF or CKi/FPi) is continuously monitored. Its validity is reported in the PFD bit of
the DHKR register.
The ST-BUS outputs (CKo0-2, FPo0-2, STo0-15 and STOHZ0-15) can be shifted to lead (advancement) or lag
(delay) the reference. The DPOA register provides this adjustment. Coarse lead or lag adjustment is programmed
via the POS6-0 bits, while fine delay (lag) control is via the SKC2-0 bits.
2.9.2
DPLL Freerun mode is selected by the setting in Table 14. In Freerun mode, the DPLL is not synchronized to the
reference. The DPLL synthesizes the internal clock MCKTDM very accurately. MCKTDM provides timing for the
TDM switching function and for the ST-BUS outputs. Since the DPLL is not synchronized to the reference, the
ST-BUS outputs are also not synchronized to the reference.
The DPLL can switch to the Freerun mode at any time. Freerun mode is typically used when a master clock
source is required, or immediately following system power-up before network synchronization is achieved. If a
ZL50011 is to be operated exclusively in Freerun mode, then its ST-BUS output clock and frame pulse must be
used as the ST-BUS input clock and frame pulse to all TDM devices in the system, including the device itself.
DPLL Master Mode
DPLL Freerun Mode
Bit 14 of CR
0
0
1
Table 14 - DPLL Operating Mode Settings
Zarlink Semiconductor Inc.
Bit 0 of DOM
ZL50011
1 or 0
0
1
33
Freerun mode
Bypass mode
Master mode
Mode
Data Sheet