PIC24FJ128GA MICROCHIP [Microchip Technology], PIC24FJ128GA Datasheet - Page 55

• Manufacturer Part Number: PIC24FJ128GA
• Description: General Purpose, 16-Bit Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 5-1:
5.1
If clock switching is enabled, the system clock source
at device Reset is chosen as shown in Table 5-2. If
clock switching is disabled, the system clock source is
always selected according to the oscillator Configura-
tion bits. Refer to 7.0 “Oscillator Configuration” for
further details.
TABLE 5-2:
© 2006 Microchip Technology Inc.
TRAPR (RCON<15>)
IOPR (RCON<14>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
Note: All Reset flag bits may be set or cleared by the user software.
Reset Type
WDTR
MCLR
SWR
POR
BOR
Clock Source Selection at Reset
Flag Bit
Oscillator Configuration Bits
(FNOSC2:FNOSC0)
COSC Control bits
(OSCCON<14:12>)
RESET FLAG BIT OPERATION
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
Trap conflict event
Illegal opcode or uninitialized W register access
MCLR Reset
RESET instruction
WDT time-out
PWRSAV #SLEEP instruction
PWRSAV #IDLE instruction
POR, BOR
POR
Setting Event
Preliminary
PIC24FJ128GA FAMILY
5.2
The Reset times for various types of device Reset are
summarized in Table 5-3. Note that the system Reset
signal, SYSRST, is released after the POR and PWRT
delay times expire.
The time that the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
Device Reset Times
POR
POR
POR
POR
PWRSAV instruction, POR
POR
POR
—
—
Clearing Event
DS39747C-page 53