PIC24FJ128GA MICROCHIP [Microchip Technology], PIC24FJ128GA Datasheet - Page 36

• Manufacturer Part Number: PIC24FJ128GA
• Description: General Purpose, 16-Bit Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 3-11:
TABLE 3-12:
TABLE 3-13:
TABLE 3-14:
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
SPI2STAT
SPI2CON1
SPI2CON2
SPI2BUF
Legend:
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
Legend:
U2MODE
U2STA
U2TXREG
U2RXREG
U2BRG
Legend:
File Name
File Name
File Name
File Name
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
Addr
Addr
0240
0242
0244
0248
Addr
0220
0222
0224
0226
0228
0260
0262
0264
0268
0230
0232
0234
0236
0238
UART1 REGISTER MAP
UTXISEL1
UART2 REGISTER MAP
SPI1 REGISTER MAP
SPI2 REGISTER MAP
UTXISEL1
UARTEN
UARTEN
FRMEN
FRMEN
SPIEN
SPIEN
Bit 15
Bit 15
Bit 15
Bit 15
—
—
—
—
—
—
SPIFSD
SPIFSD
UTXINV
UTXINV
Bit 14
Bit 14
Bit 14
Bit 14
—
—
—
—
—
—
—
—
—
—
SPIFPOL
SPIFPOL
UTXISEL0
SPISIDL
SPISIDL
UTXISEL0
Bit 13
Bit 13
Bit 13
USIDL
Bit 13
USIDL
—
—
—
—
—
—
DISSCK
DISSCK
Bit 12
Bit 12
Bit 12
Bit 12
IREN
IREN
—
—
—
—
—
—
—
—
—
—
UTXBRK
UTXBRK
DISSDO
RTSMD
DISSDO
RTSMD
Bit 11
Bit 11
Bit 11
Bit 11
—
—
—
—
—
—
—
—
SPIBEC2 SPIBEC1 SPIBEC0
SPIBEC2 SPIBEC1 SPIBEC0
MODE16
MODE16
UTXEN
UTXEN
Bit 10
Bit 10
Bit 10
Bit 10
—
—
—
—
—
—
—
—
UTXBF
UTXBF
UEN1
Bit 9
UEN1
Bit 9
Bit 9
SMP
Bit 9
SMP
—
—
—
—
—
—
SPI1 Transmit and Receive Buffer
SPI2 Transmit and Receive Buffer
Baud Rate Generator Prescaler
Baud Rate Generator Prescaler
TRMT
UEN0
Bit 8
UEN0
TRMT
Bit 8
Bit 8
Bit 8
CKE
CKE
—
—
URXISEL1 URXISEL0
URXISEL1 URXISEL0
WAKE
Bit 7
WAKE
SSEN
SSEN
Bit 7
Bit 7
Bit 7
—
—
—
—
SPIROV
SPIROV
LPBACK
LPBACK
Bit 6
Bit 6
CKP
CKP
Bit 6
—
—
Bit 6
MSTEN
MSTEN
ADDEN
ABAUD
Bit 5
Bit 5
ABAUD
ADDEN
Bit 5
—
—
—
—
Bit 5
Transmit Register
Receive Register
Transmit Register
Receive Register
SPRE2
SPRE2
Bit 4
RXINV
Bit 4
RIDLE
RXINV
RIDLE
Bit 4
—
—
—
—
Bit 4
SPRE1
SPRE1
Bit 3
Bit 3
BRGH
PERR
BRGH
Bit 3
PERR
—
—
Bit 3
—
—
PDSEL1
SPRE0
SPRE0
PDSEL1
FERR
Bit 2
Bit 2
Bit 2
FERR
Bit 2
—
—
—
—
PDSEL0
SPITBF
SPITBF
PDSEL0
PPRE1
PPRE1
SPIFE
OERR
SPIFE
OERR
Bit 1
Bit 1
Bit 1
Bit 1
URXDA
SPIBEN
SPIRBF
SPIBEN
SPIRBF
URXDA
STSEL
PPRE0
STSEL
PPRE0
Bit 0
Bit 0
Bit 0
Bit 0
Resets
Resets
Resets
Resets
0000
0110
xxxx
0000
0000
0000
0110
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
All
All
All
All