PIC24FJ128GA MICROCHIP [Microchip Technology], PIC24FJ128GA Datasheet - Page 161

• Manufacturer Part Number: PIC24FJ128GA
• Description: General Purpose, 16-Bit Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

18.3
• Configurable from half second to one year
• Enabled using the ALRMEN bit (ALCFGRPT<7>,
• One-time alarm and repeat alarm options
18.3.1
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. Writes to
ALRMVALH:ALRMVALL should only take place when
ALRMEN = 0.
As shown in Figure 18-2, the interval selection of the
alarm is
(ALCFGRPT<13:10>). These bits determine which and
how many digits of the alarm must match the clock
value for the alarm to occur. The alarm can also be con-
figured to repeat based on a preconfigured interval.
The amount of times this occurs once the alarm is
enabled is stored in the lower half of the ALCFGRPT
register.
When ALCFGRPT = 00 and CHIME bit = 0
(ALCFGRPT<14>), the repeat function is disabled and
only a single alarm will occur. The alarm can be
repeated up to 255 times by loading the lower half of
the ALCFGRPT register with FFh.
FIGURE 18-2:
© 2006 Microchip Technology Inc.
Register 18-3)
available
Alarm
Note 1:
0000 – Every half second
0001 – Every second
0010 – Every 10 seconds
0011 – Every minute
0100 – Every 10 minutes
0101 – Every hour
0110 – Every day
0111 – Every week
1000 – Every month
1001 – Every year
CONFIGURING THE ALARM
configured
(AMASK3:AMASK0)
Alarm Mask Setting
Annually, except when configured for February 29.
ALARM MASK SETTINGS
through
(1)
the
AMASK
Day of
Week
the
d
Preliminary
bits
Month
m
PIC24FJ128GA FAMILY
m
After each alarm is issued, the ALCFGRPT register is
decremented by one. Once the register has reached
‘00’, the alarm will be issued one last time, after which
the ALRMEN bit will be cleared automatically and the
alarm will turn off. Indefinite repetition of the alarm can
occur if the CHIME bit = 1. Instead of the alarm being
disabled when the ALCFGRPT register reaches ‘00’, it
will roll over to FF and continue counting indefinitely
when CHIME = 1.
18.3.2
At every alarm event an interrupt is generated. In addi-
tion, an alarm pulse output is provided that operates at
half the frequency of the alarm. This output is
completely synchronous to the RTCC clock and can be
used as a trigger clock to other peripherals.
Note:
d
d
Day
d
d
ALARM INTERRUPT
Changing any of the registers, other then
the RCFGCAL and ALCFGRPT registers
and the CHIME bit while the alarm is
enabled (ALRMEN = 1), can result in a
false alarm event leading to a false alarm
interrupt. To avoid a false alarm event, the
timer and alarm values should only be
changed while the alarm is disabled
(ALRMEN = 0). It is recommended that the
ALCFGRPT register and CHIME bit be
changed when RTCSYNC = 0.
Hours
h
h
h
h
h
h
h
h
Minutes
m
m
m
m
m
m
m
m
m
m
m
DS39747C-page 159
Seconds
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s