PIC24FJ128GA MICROCHIP [Microchip Technology], PIC24FJ128GA Datasheet - Page 54

• Manufacturer Part Number: PIC24FJ128GA
• Description: General Purpose, 16-Bit Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

PIC24FJ128GA FAMILY
REGISTER 5-1:
DS39747C-page 52
Upper Byte:
bit 15
bit 15
bit 14
bit 13-10 Unimplemented: Read as ‘0’
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TRAPR
R/W-0
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode, or uninitialized W register used as an Address
0 = An illegal opcode or uninitialized W Reset has not occurred
CM: Configuration Word Mismatch Reset Flag bit
1 = A Configuration Word Mismatch Reset has occurred
0 = A Configuration Word Mismatch Reset has not occurred
VREGS: Voltage Regulator Standby Enable bit
1 = Regulator remains active during Sleep
0 = Regulator goes to standby during Sleep
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit
1 = WDT is enabled
0 = WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
SLEEP: Wake From Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
IDLE: Wake-up From Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred. Note that BOR is also set after Power-on Reset.
0 = A Brown-out Reset has not occurred
POR: Power-on Reset Flag bit
1 = A Power-up Reset has occurred
0 = A Power-up Reset has not occurred
Legend:
R = Readable bit
-n = Value at POR
Note:
Note:
IOPUWR
R/W-0
Pointer caused a Reset
Lower Byte:
bit 7
R/W-0
EXTR
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software
does not cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless
of the SWDTEN bit setting.
RCON: RESET CONTROL REGISTER
U-0
—
R/W-0
SWR
U-0
—
W = Writable bit
‘1’ = Bit is set
SWDTEN
R/W-0
Preliminary
U-0
—
WDTO
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SLEEP
R/W-0
R/W-0
CM
R/W-0
IDLE
© 2006 Microchip Technology Inc.
VREGS
R/W-0
x = Bit is unknown
bit 8
R/W-1
BOR
R/W-1
POR
bit 0