PIC24FJ128GA MICROCHIP [Microchip Technology], PIC24FJ128GA Datasheet - Page 130

• Manufacturer Part Number: PIC24FJ128GA
• Description: General Purpose, 16-Bit Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

PIC24FJ128GA FAMILY
REGISTER 15-2:
DS39747C-page 128
bit 15
bit 14
bit 13-11 Unimplemented: Read as ‘0’
bit 10
bit 9
bit 8
bit 7
bit 6
.
Upper Byte:
bit 15
ACKSTAT
R-0 HSC
ACKSTAT: Acknowledge Status bit
(When operating as I
1 = NACK received from slave
0 = ACK received from slave
Hardware set or clear at end of slave Acknowledge.
TRSTAT: Transmit Status bit
(When operating as I
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at beginning of master transmission.
Hardware clear at end of slave Acknowledge.
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address.
Hardware clear at Stop detection.
ADD10: 10-bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address.
Hardware clear at Stop detection.
IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register failed because the I
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CRSR to I2CxRCV (cleared by software).
Legend:
R = Readable bit
-n = Value at POR
R-0 HSC
TRSTAT
Lower Byte:
bit 7
R/C-0 HS
IWCOL
I2CxSTAT: I2Cx STATUS REGISTER
U-0
—
R/C-0 HS
2
2
C master. Applicable to master transmit operation.)
C master. Applicable to master transmit operation.)
I2COV
C = Clearable bit
‘1’ = Bit is set
U-0
—
R-0 HSC
D/A
Preliminary
U-0
—
R/C-0 HSC R/C-0 HSC
U = Unimplemented bit, read as ‘0’
HS = Set in Hardware
‘0’ = Bit is cleared
P
R/C-0 HS
BCL
S
2
R-0 HSC
GCSTAT
C module is busy
R-0 HSC
HSC = Hardware Set/Cleared
x = Bit is unknown
R/W
© 2006 Microchip Technology Inc.
R-0 HSC
ADD10
R-0 HSC
bit 8
RBF
R-0 HSC
TBF
bit 0