PIC18F2423 MICROCHIP [Microchip Technology], PIC18F2423 Datasheet - Page 270

• Manufacturer Part Number: PIC18F2423
• Description: 28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2423/2523/4423/4523
23.5.1
Any location in program memory may be read from, or
written to, using the table read and table write instruc-
tions. The device ID may be read with table reads. The
Configuration registers may be read and written with
the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTn Configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the EBTRn
bit set to ‘0’, a table read instruction that executes from
within that block is allowed to read. A table read instruc-
FIGURE 23-6:
DS39755B-page 268
TBLPTR = 0008FFh
Results: All table writes disabled to Blockn whenever WRTn = 0
Register Values
PROGRAM MEMORY
CODE PROTECTION
PC = 001FFEh
PC = 005FFEh
TABLE WRITE (WRTn) DISALLOWED
Program Memory
Preliminary
TBLWT*
TBLWT*
tion that executes from a location outside of that block is
not allowed to read and will result in reading ‘0’s.
Figures 23-6 through 23-8 illustrate table write and table
read protection.
Note:
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
.
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
Configuration Bit Settings
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
© 2007 Microchip Technology Inc.