PIC18F2423 MICROCHIP [Microchip Technology], PIC18F2423 Datasheet - Page 264

• Manufacturer Part Number: PIC18F2423
• Description: 28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2423/2523/4423/4523
23.2
For PIC18LF2423/2523/4423/4523 devices, the WDT
is driven by the INTRC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits (OSCCON<6:4>) are changed or a clock
failure has occurred.
FIGURE 23-1:
DS39755B-page 262
Change on IRCF bits
All Device Resets
Watchdog Timer (WDT)
INTRC Source
WDTPS<3:0>
SWDTEN
WDTEN
CLRWDT
Sleep
WDT BLOCK DIAGRAM
Enable WDT
WDT Counter
÷128
4
Preliminary
Programmable Postscaler
1:1 to 1:32,768
4 ms
23.2.1
Register 23-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
Note 1: The CLRWDT and SLEEP instructions
2: Changing the setting of the IRCF bits
3: When a CLRWDT instruction is executed,
4: When the FSCM detects a clock failure
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
(OSCCON<6:4>) clears the WDT and
postscaler counts.
the postscaler count will be cleared.
and switches clock sources, the WDT and
postscaler counts are cleared.
Reset
© 2007 Microchip Technology Inc.
Wake-up from
Power-Managed
Modes
WDT
Reset