PIC18F2423 MICROCHIP [Microchip Technology], PIC18F2423 Datasheet - Page 175

• Manufacturer Part Number: PIC18F2423
• Description: 28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 17-5:
© 2007 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Note 1:
R/W-0
GCEN
2:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT/ADMSK5: Acknowledge Data bit
In Master Receive mode:
1 = Not Acknowledge
0 = Acknowledge
In Slave mode:
1 = Address masking of ADD5 enabled
0 = Address masking of ADD5 disabled
ACKEN/ADMSK4: Acknowledge Sequence Enable bit
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically
0 = Acknowledge sequence Idle
In Slave mode:
1 = Address masking of ADD4 enabled
0 = Address masking of ADD4 disabled
RCEN/ADMSK3: Receive Enable bit
In Master Receive mode:
1 = Enables Receive mode for I
0 = Receive Idle
In Slave mode:
1 = Address masking of ADD3 enabled
0 = Address masking of ADD3 disabled
PEN/ADMSK2: Stop Condition Enable bit
In Master mode:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
In Slave mode:
1 = Address masking of ADD2 enabled
0 = Address masking of ADD2 disabled
ACKSTAT
R/W-0
cleared by hardware.
SSPCON2: MSSP CONTROL REGISTER 2 (I
W = Writable bit
‘1’ = Bit is set
(1)
ADMSK5
ACKDT/
R/W-0
(2)
(1)
(1)
PIC18F2423/2523/4423/4523
ACKEN
ADMSK4
2
R/W-0
C
Preliminary
(1)
/
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RCEN
ADMSK3
2
R/W-0
C module is active, these bits may not be set (no
(1)
/
2
C™ MODE)
ADMSK2
PEN
R/W-0
(1)
/
x = Bit is unknown
ADMSK1
RSEN
R/W-0
(1)
DS39755B-page 173
/
SEN
R/W-0
(1)
bit 0