PIC18F2423 MICROCHIP [Microchip Technology], PIC18F2423 Datasheet - Page 178

• Manufacturer Part Number: PIC18F2423
• Description: 28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2423/2523/4423/4523
17.4.3.2
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-bit mode and up to
63 addresses in 10-bit mode (see Example 17-2).
The I
masking is used or not. However, when address
masking is used, the I
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking SSPBUF.
• 7-Bit Address mode
EXAMPLE 17-2:
DS39755B-page 176
Address mask bits, ADMSK<5:1>, mask the
corresponding address bits in the SSPADD
register. For any ADMSK bits that are active
(ADMSK<n> = 1), the corresponding address bit
is ignored (ADD<n> = x). For the module to issue
an address Acknowledge, it is sufficient to match
only on addresses that do not have an active
address mask.
7-bit addressing:
10-bit addressing:
2
C slave behaves the same way whether address
SSPxADD<7:1> = 1010 0000
ADMSK<5:1>
Addresses Acknowledged = 0xA0, 0xA2, 0xA4, 0xA6
SSPxADD<7:0> = 1010 0000 (The two MSbs are ignored in this example since they are not affected.)
ADMSK<5:1>
Addresses Acknowledged = 0xA0, 0xA1, 0xA2, 0xA3
The upper two bits are not affected by the address masking.
Address Masking
ADDRESS MASKING
2
C slave can Acknowledge
= 00 111
= 00 111
0xA8, 0xAA, 0xAC, 0xAE
0xA4, 0xA5, 0xA6, 0xA7
0xA8, 0xA9, 0xAA 0xAB
0xAC, 0xAD, 0xAE, 0xAF
Preliminary
• 10-Bit Address mode
Address mask bits, ADMSK<5:2>, mask the
corresponding address bits in the SSPADD register.
In addition, ADMSK<1> simultaneously masks the
two LSBs of the address, ADD<1:0>. For any
ADMSK bits that are active (ADMSK<n> = 1), the
corresponding address bit is ignored (ADD<n> = x).
Also note that although in 10-Bit Addressing mode
the upper address bits reuse part of the SSPADD
register bits, the address mask bits do not interact
with those bits. They only affect the lower address
bits.
Note 1: ADMSK<1>
2: The two Most Significant bits of the
Significant bits of the address.
address are not affected by address
masking.
© 2007 Microchip Technology Inc.
masks
the
two
Least