PIC18F2423 MICROCHIP [Microchip Technology], PIC18F2423 Datasheet - Page 176

• Manufacturer Part Number: PIC18F2423
• Description: 28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2423/2523/4423/4523
REGISTER 17-5:
REGISTER 17-6:
DS39755B-page 174
bit 1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
R/W-0
ADD7
2:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
MSSP Address register in I
RSEN/ADMSK1: Repeated Start Condition Enable bit
In Master mode:
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
In Slave mode (7-Bit Address mode):
1 = Address masking of ADD1 enabled
0 = Address masking of ADD1 disabled
In Slave mode (10-Bit Address mode):
1 = Address masking of ADD1 and ADD0 enabled
0 = Address masking of ADD1 and ADD0 disabled
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
ADD<7:0>: MSSP Address bits
R/W-0
ADD6
SSPCON2: MSSP CONTROL REGISTER 2 (I
SSPADD: MSSP ADDRESS REGISTER
W = Writable bit
‘1’ = Bit is set
(1)
R/W-0
ADD5
2
C™ Slave mode. MSSP Baud Rate register in I
R/W-0
ADD4
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
2
R/W-0
ADD3
C module is active, these bits may not be set (no
(1)
(1)
2
C™ MODE) (CONTINUED)
R/W-0
ADD2
2
© 2007 Microchip Technology Inc.
C Master mode.
x = Bit is unknown
R/W-0
ADD1
R/W-0
ADD0
bit 0