PIC18F2423 MICROCHIP [Microchip Technology], PIC18F2423 Datasheet - Page 172

• Manufacturer Part Number: PIC18F2423
• Description: 28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2423/2523/4423/4523
17.4
The MSSP module in I
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
FIGURE 17-7:
DS39755B-page 170
Note:
SCL
SDA
I
Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list
of multiplexed functions.
2
C Mode
Read
Shift
Clock
MSb
Address Mask
Stop bit Detect
Match Detect
SSPADD reg
MSSP BLOCK DIAGRAM
(I
SSPBUF reg
SSPSR reg
Start and
2
2
C mode fully implements all
C™ MODE)
LSb
Write
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
Internal
Data Bus
Preliminary
17.4.1
The MSSP module has six registers for I
These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
• MSSP Shift Register (SSPSR) – Not directly
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address when
the MSSP is configured in I
MSSP is configured in Master mode, the lower seven
bits of SSPADD act as the Baud Rate Generator reload
value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
(SSPBUF)
accessible
REGISTERS
© 2007 Microchip Technology Inc.
2
2
C mode operation. The
C Slave mode. When the
2
C operation.