PIC18F2423 MICROCHIP [Microchip Technology], PIC18F2423 Datasheet - Page 163
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PIC18F2423
Manufacturer Part Number
PIC18F2423
Description
28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2423.pdf
(392 pages)
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17.0
17.1
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
The I
hardware:
• Master mode
• Multi-Master mode
• Slave mode (with address masking for both 10-bit
17.2
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual Configuration bits
differ significantly depending on whether the MSSP
module is operated in SPI or I
Additional details are provided under the individual
sections.
© 2007 Microchip Technology Inc.
- Full Master mode
- Slave mode (with general address call)
and 7-bit addressing)
2
C interface supports the following modes in
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
Control Registers
2
C)
2
C mode.
PIC18F2423/2523/4423/4523
Preliminary
17.3
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes
communication, typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/SS/HLVDIN/
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1:
Note:
C2OUT
SCK
SDO
SDI
SS
Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
SPI Mode
of
SPI
Read
SS Control
Enable
Select
SMP:CKE
are
Edge
bit 0
Select
Edge
MSSP BLOCK DIAGRAM
(SPI MODE)
Data to TX/RX in SSPSR
TRIS bit
SSPBUF reg
SSPM3:SSPM0
2
supported.
SSPSR reg
Clock Select
4
2
DS39755B-page 161
(
Prescaler
4, 16, 64
TMR2 Output
To
Write
Clock
Shift
Data Bus
Internal
2
accomplish
T
OSC
)
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