KSZ8895MQ_12 MICREL [Micrel Semiconductor], KSZ8895MQ_12 Datasheet - Page 72

• Manufacturer Part Number: KSZ8895MQ_12
• Description: Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
Port Registers (Continued)
Note:
Port Control 12 and 13, 14 and Port Status 1,2 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition.
Advanced Control Registers
Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in MAC pause control frames.
Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or the MIB counters.
March 2012
Address
2-0
Address
Register 104 (0x68): MAC Address Register 0
7-0
Register 105 (0x69): MAC Address Register 1
7-0
Register 106 (0x6A): MAC Address Register 2
7-0
Register 107 (0x6B): MAC Address Register 3
7-0
Register 108 (0x6C): MAC Address Register 4
7-0
Register 109 (0X6D): MAC Address Register 5
7-0
Address
Register 110 (0x6E): Indirect Access Control 0
7-5
4
3-2
Name
Port Operation Mode
Indication
Name
MACA[47:40]
MACA[39:32]
MACA[31:24]
MACA[23:16]
MACA[15:8]
MACA[7:0]
Reserved
Read High Write Low
Table Select
Name
Description
Description
Indicate the current state of port operation mode:
[000] = Reseved
[001] = still in auto-negotiation
[010] = 10BASE-T half duplex
[011] = 100BASE-TX half duplex
[100] = Reserved
[101] = 10BASE-T full duplex
[110] = 100BASE-TX full duplex
[111] = Reserved
Description
Reserved.
1, read cycle.
0, write cycle.
00 = static mac address table selected.
01 = VLAN table selected.
10 = dynamic address table selected.
11 = MIB counter selected.
72
Mode
Mode
R/W
R/W
R/W
R/W
R/W
R/W
Mode
RO
R/W
R/W
R/W
KSZ8895MQ/RQ/FMQ
M9999-032612-1.5
Default
Default
Default
0xA1
0x00
0x10
001
0xff
0xff
0xff
000
0
0