KSZ8895MQ_12 MICREL [Micrel Semiconductor], KSZ8895MQ_12 Datasheet
KSZ8895MQ_12
Related parts for KSZ8895MQ_12
KSZ8895MQ_12 Summary of contents
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General Description The KSZ8895MQ/RQ/FMQ is a highly-integrated, Layer 2-managed, five-port switch with numerous features designed to reduce system cost. Intended for cost-sensitive 10/100Mbps five-port switch systems with low power consumption, on-chip termination, and internal core power controllers, high-performance memory bandwidth ...
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Micrel, Inc. Features Advanced Switch Features IEEE 802.1q VLAN support for up to 128 active VLAN groups (full-range 4096 of VLAN IDs). Static MAC table supports entries. VLAN ID tag/untag options, per port basis ...
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Micrel, Inc. Confidential Applications Typical VoIP Phone Set-top/Game Box Automotive Industrial Control Ordering Information Part Number Temperature Range KSZ8895MQ KSZ8895MQI -40°C to +85°C KSZ8895RQ KSZ8895RQI -40°C to +85°C (1) KSZ8895FMQ (1) KSZ8895FMQI -40°C to +85°C ...
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Micrel, Inc. Contents Pin Configuration ..........................................................................................................................................................13 Pin Description ..............................................................................................................................................................14 Pin for Strap-in Options................................................................................................................................................21 Introduction ...................................................................................................................................................................24 Functional Overview: Physical Layer Transceiver ....................................................................................................24 100BASE-TX Transmit ...............................................................................................................................................24 100BASE-TX Receive ................................................................................................................................................24 PLL Clock Synthesizer................................................................................................................................................25 Scrambler/Descrambler (100BASE-TX only) .............................................................................................................25 100BASE-FX Operation..............................................................................................................................................25 100BASE-FX Signal Detection ...................................................................................................................................25 ...
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Micrel, Inc. Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ......................................................................................37 Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ .................................................................................37 SNI Interface Operation ..............................................................................................................................................40 Advanced Functionality................................................................................................................................................41 QoS Priority Support...................................................................................................................................................41 Port-Based Priority..................................................................................................................................................41 802.1p-Based Priority .............................................................................................................................................41 DiffServ-Based Priority ...........................................................................................................................................42 Spanning ...
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Micrel, Inc. Register 32 (0x20): Port 2 Control 0.......................................................................................................................64 Register 48 (0x30): Port 3 Control 0.......................................................................................................................64 Register 64 (0x40): Port 4 Control 0.......................................................................................................................64 Register 80 (0x50): Port 5 Control 0.......................................................................................................................64 Register 17 (0x11): Port 1 Control 1.......................................................................................................................65 Register 33 (0x21): ...
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Micrel, Inc. Register 92 (0x5C): Port 5 Control 5 ......................................................................................................................69 Register 29 (0x1D): Port 1 Control 6 ......................................................................................................................70 Register 45 (0x2D): Port 2 Control 6 ......................................................................................................................70 Register 61 (0x3D): Port 3 Control 6 ......................................................................................................................70 Register 77 (0x4D): Port 4 Control ...
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Micrel, Inc. Register 144 (0x90): TOS Priority Control Register 0 ............................................................................................77 Register 145 (0x91): TOS Priority Control Register 1 ............................................................................................78 Register 146 (0x92): TOS Priority Control Register 2 ............................................................................................78 Register 147 (0x93): TOS Priority Control Register 3 ............................................................................................78 Register 148 ...
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Micrel, Inc. Register 229 (0xE5): Port 4 Control 13 ..................................................................................................................83 Register 245 (0xF5): Port 5 Control 13...................................................................................................................83 Register 182 (0xB6): Port 1 Rate Limit Control ......................................................................................................83 Register 198 (0xC6): Port 2 Rate Limit Control......................................................................................................83 Register 214 (0xD6): Port 3 Rate ...
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Micrel, Inc. Register 222 (0xDE) : Port 3 Queue 3 Egress Limit Control 4 ...............................................................................86 Register 238 (0xEE): Port 4 Queue 3 Egress Limit Control 4 ................................................................................86 Register 254 (0xFE): Port 5 Queue 3 Egress Limit Control 4 ................................................................................86 Data ...
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Micrel, Inc. List of Figures Figure 1. Typical Straight Cable Connection ............................................................................................................... 26 Figure 2. Typical Crossover Cable Connection ........................................................................................................... 27 Figure 3. Auto-Negotiation ........................................................................................................................................... 28 Figure 4. Destination Address Lookup Flow Chart, Stage 1 ........................................................................................ 33 Figure 5. Destination ...
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Micrel, Inc. List of Tables Table 1. MDI/MDI-X Pin Definitions ............................................................................................................................. 26 Table 2. Internal Function Block Status ........................................................................................................................ 29 Table 3. Port 5 PHY P5-MII/RMII Signals .................................................................................................................... 36 Table 4. Switch MAC5 MII Signals............................................................................................................................... 37 Table 5. Port 5 ...
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Micrel, Inc. Pin Configuration 103 LED2-0 104 LED1-2 105 LED1-1 106 LED1-0 107 MDC 108 MDIO 109 SPIQ 110 SPIC/SCL 111 SPID/SDA 112 SPIS_N 113 PS1 114 PS0 115 RST_N 116 GNDD 117 VDDC 118 TESTEN 119 SCANEN 120 NC ...
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Micrel, Inc. Pin Description Pin Number Pin Name 1 MDI-XDIS 2 GNDA 3 VDDAR 4 RXP1 5 RXM1 6 GNDA 7 TXP1 8 TXM1 9 VDDAT 10 RXP2 11 RXM2 12 GNDA 13 TXP2 14 TXM2 15 VDDAR 16 GNDA ...
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Micrel, Inc. Pin Description (Continued) Pin Number Pin Name 39 FXSD4 PWRDN_N 48 INTR_N 49 GNDD 50 VDDC 51 PMTXEN 52 PMTXD3 53 PMTXD2 54 ...
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Micrel, Inc. Pin Description (Continued) Pin Number Pin Name 64 PMRXD1 65 PMRXD0 66 PMRXER 67 PCRS 68 PCOL 69 SMTXEN 70 SMTXD3 71 SMTXD2 72 SMTXD1 73 SMTXD0 74 SMTXER SMTXC/SMREFCLK 75 76 GNDD 77 VDDIO March 2012 (1) ...
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Micrel, Inc. Pin Description (Continued) Pin Number Pin Name 78 SMRXC 79 SMRXDV/SMCRSDV 80 SMRXD3 81 SMRXD2 82 SMRXD1 83 SMRXD0 84 SCOL 85 SCRS March 2012 (1) Type Port MQ/FMQ: Port 5 Switch MII receive clock, Input: SW5-MII MAC ...
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Micrel, Inc. Pin Description (Continued) Pin Number Pin Name 86 SCONF1 87 SCONF0 88 GNDD 89 VDDC 90 LED5-2 91 LED5-1 92 LED5-0 93 LED4-2 94 LED4-1 95 LED4-0 96 LED3-2 97 LED3-1 98 LED3-0 99 GNDD March 2012 (1) ...
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Micrel, Inc. Pin Description (Continued) Pin Number Pin Name 100 VDDIO 101 LED2-2 102 LED2-1 103 LED2-0 104 LED1-2 105 LED1-1 106 LED1-0 107 MDC 108 MDIO 109 SPIQ 110 SPIC/SCL 111 SSPID/SDA 112 SPIS_N March 2012 (1) (2) Type ...
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Micrel, Inc. Pin Description (Continued) Pin Number Pin Name 113 PS1 114 PS0 115 RST_N 116 GNDD 117 VDDC 118 TESTEN 119 SCANEN 120 NC 121 X1 122 X2 123 NC 124 NC 125 LDO_O 126 IN_PWR_SEL 127 GNDA 128 ...
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Micrel, Inc. Pin for Strap-in Options The KSZ8895MQ/RQ/FMQ can function as a managed switch or an unmanaged switch EEPROM or micro- controller exists, then the KSZ8895MQ/RQ/FMQ will operate from its default setting. The strap-in option pins can be ...
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Micrel, Inc. Pin # Pin Name PU/PD 83 SMRXD0 86 SCONF1 87 SCONF0 90 LED5-2 91 LED5-1 92 LED5-0 95 LED4-0 98 LED3-0 March 2012 (1) (1) Description Switch MII receive bit 0. Strap option: LED mode PD (default) = ...
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Micrel, Inc. Pin # Pin Name PU/PD 101 LED2-2 102 LED2-1 105 LED1-1 106 LED1-0 113 PS1 114 PS0 128 TEST2 Notes connect. IPD = Input w/internal pull-down. IPD/O = Input w/internal pull-down during reset, output ...
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Micrel, Inc. Introduction The KSZ8895MQ/RQ/FMQ contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode five-port integrated switch. ...
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Micrel, Inc. PLL Clock Synthesizer The KSZ8895MQ/RQ/FMQ generates 125MHz, 83MHz, 41MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. Scrambler/Descrambler (100BASE-TX only) The purpose of the scrambler is to spread ...
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Micrel, Inc. RJ-45 Pins Straight Cable A straight cable connects an MDI device to an MDI-X device MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and ...
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Micrel, Inc. Crossover Cable A crossover cable connects an MDI device to another MDI device MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). ...
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Micrel, Inc. March 2012 Figure 3. Auto-Negotiation 28 KSZ8895MQ/RQ/FMQ M9999-032612-1.5 ...
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Micrel, Inc. On-chip Termination Resistors The KSZ8895MQ/RQ/FMQ reduces the board cost and simplifies the board layout by using on-chip termination resistors for all ports and RX/TX differential pairs without the external termination resistors. The combination of the on-chip termination and ...
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Micrel, Inc. Energy Detect Mode Energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8895MQ/FMQ port is not connected to an active link partner. In this mode, the device will save ...
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Micrel, Inc. Migration The internal look-up engine also monitors whether a station is moved. If this occurs, it updates the table accordingly. Migration happens when the following conditions are met: The received packet’ the table but ...
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Micrel, Inc. Flow Control The KSZ8895MQ/RQ/FMQ supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KSZ8895MQ/RQ/FMQ receives a pause control frame, the KSZ8895MQ/RQ/FMQ will not transmit the next normal frame until ...
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Micrel, Inc. Figure 4. Destination Address Lookup Flow Chart, Stage 1 March 2012 33 KSZ8895MQ/RQ/FMQ M9999-032612-1.5 ...
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Micrel, Inc. Figure 5. Destination Address Resolution Flow Chart, Stage 2 The KSZ8895MQ/RQ/FMQ will not forward the following packets: 1. Error packets These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors. 2. IEEE802.3x ...
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Micrel, Inc. Half-Duplex Back Pressure The KSZ8895MQ/RQ/FMQ also provides a half-duplex back pressure option (note: this is not in IEEE 802.3 standards). The activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure ...
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Micrel, Inc. MII Interface Operation The media-independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. The KSZ8895MQ/RQ/FMQ provides two such interfaces. The P5-MII interface is used to ...
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Micrel, Inc. Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ Table 4 shows two connection manners: 1. The first is an external MAC connects to SW5-MII PHY mode. 2. The second is an external PHY connects to SW5-MII MAC ...
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Micrel, Inc. Supports 10Mbps and 100Mbps data rates. Uses a single 50MHz clock reference (provided internally or externally): in internal mode, the chip provides a reference clock from the SMRXC pin to the SMTXC pin and provides the ...
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Micrel, Inc. SW5-RMII MAC to MAC Connection (‘PHY mode’) KSZ8895RQ External KSZ8895RQ SW Signal MAC SW5-RMII Type Output (clock mode with 50MHz) REF_CLK SMRXC (Normal mode without connection) SMRXDV CRS_DV Output /SMCRSDV RXD1 SMRXD[1] Output RXD0 SMRXD[0] Output TX_EN SMTXEN ...
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Micrel, Inc. SNI Interface Operation The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing. This interface can be directly connected to these types of devices. The signals are divided into two groups, one ...
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Micrel, Inc. Advanced Functionality QoS Priority Support The KSZ8895MQ/RQ/FMQ provides Quality of Service (QoS) for applications such as VoIP and video conferencing. The KSZ8895MQ/RQ/FMQ offers one, two, or four priority queues per port by setting the port registers xxx control ...
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Micrel, Inc. The KSZ8895MQ/RQ/FMQ provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, consisting of the two-byte VLAN Protocol ID (VPID) and the two-byte Tag Control Information field (TCI), is ...
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Micrel, Inc. BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. ...
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Micrel, Inc. Tail Tagging Mode The Tail Tag is only seen and used by the Port 5 interface, which should be connected to a processor by SW5-MII interface. The one byte tail tagging is used to indicate the source/destination port ...
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Micrel, Inc. IGMP Support There are two parts involved to support the Internet Group Management Protocol (IGMP) in Layer 2. The first part is IGMP snooping, the second part is this IGMP packet to be sent back to the subscribed ...
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Micrel, Inc. DA found in USE FID Static MAC table Flag Not care No Do Not care Yes 0 Yes 1 Yes 1 Yes 1 SA+FID found in Action Dynamic MAC table No The SA+FID will be learned ...
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Micrel, Inc. Egress Rate Limit For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic. Interframe gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The ...
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Micrel, Inc. Figure 8. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram To configure the KSZ8895MQ/RQ/FMQ with a pre-configured EEPROM use the following steps the board level, connect pin 110 on the KSZ8895MQ/RQ/FMQ to the SCL pin on the EEPROM. Connect ...
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Micrel, Inc. To use the KSZ8895MQ/RQ/FMQ SPI the board level, connect KSZ8895MQ/RQ/FMQ pins as follows: KSZ8895MQ/RQ/FMQ KSZ8895MQ/RQ/FMQ Pin Number Signal Name 112 SPIS_N 110 SPIC 111 SPID 109 SPIQ 2. Set the input signals PS[1:0] (pins 113 and ...
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Micrel, Inc. SPIS_N SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ Byte 2 SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N SPIC SPID X X ...
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Micrel, Inc. MII Management Interface (MIIM) The KSZ8895MQ/RQ/FMQ supports the standard IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8895MQ/RQ/FMQ. An ...
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Micrel, Inc. SMI register Read access is selected when OP Code is set to “10” and bits [2:1] of the PHY address is set to ‘11’. The 8-bit register address is the concatenation of {PHY address bits [4:3], PHY address ...
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Micrel, Inc. Register Description Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers. 2-13 0x02-0x0D Global Control Registers. 14-15 0x0E-0x0F Power Down Management Control Registers. 16-20 0x10-0x14 Port 1 Control Registers. 21-23 0x15-0x17 Port 1 Reserved (Factory Test Registers). 24-31 ...
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Micrel, Inc. Register Description (Continued) Offset Decimal Hex Description 192-206 0xC0-0xCE Port 2 Control Registers. 207 0xCF Reserved (Factory Testing Register). 208-222 0xD0-0xDE Port 3 Control Registers. 223 0xDF Reserved (Factory Testing Register). 224-238 0xE0-0xEE Port 4 Control Registers. 239 ...
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Micrel, Inc. Global Registers Address Name Register 0 (0x00): Chip ID0 7-0 Family ID Register 1 (0x01): Chip ID1 / Start Switch 7-4 Chip ID 3-1 Revision ID 0 Start Switch Register 2 (0x02): Global Control 0 7 New Back-off ...
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Micrel, Inc. Global Registers (Continued) Address Name 3 Enable PHY MII/RMII 2 Reserved 1 UNH Mode 0 Link Change Age Register 3 (0x03): Global Control 1 7 Pass All Frames 6 2K Byte packet support IEEE 802.3x Transmit 5 Flow ...
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Micrel, Inc. Global Registers (Continued) Address Name Frame Length Field 3 Check 2 Aging Enable 1 Fast age Enable Aggressive Back Off 0 Enable Register 4 (0x04): Global Control 2 Unicast Port-VLAN 7 Mismatch Discard Multicast Storm 6 Protection Disable ...
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Micrel, Inc. Global Registers (Continued) Address Name Flow Control and Back 4 Pressure fair Mode No Excessive 3 Collision Drop 2 Huge Packet Support Legal Maximum Packet 1 Size Check Disable 0 Reserved Register 5 (0x05): Global Control 3 7 ...
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Micrel, Inc. Global Registers (Continued) Address Name Enable Pre-Tag on 4 Switch SW5- MII/TMI/RMIII Interface 3-2 Reserved 1 Enable “Tag” Mask 0 Sniff Mode Select Register 6 (0x07): Global Control 4 Switch SW5-MII/RMII 7 Back Pressure Enable Switch SW5-MII/RMII 6 ...
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Micrel, Inc. Global Registers (Continued) Address Name Switch SW5-MII/RMII 4 Speed 3 Null VID Replacement Broadcast Storm 2-0 Protection Rate Bit[10:8] Register 7 (0x07): Global Control 5 Broadcast Storm 7-0 Protection Rate Bit[7:0] Register 8 (0x08): Global Control 6 7-0 ...
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Micrel, Inc. Global Registers (Continued) Address Name Register 10 (0x0A): Global Control 8 7-0 Factory Testing Register 11 (0x0B): Global Control 9 7 Reversed Port 5 SW5- RMII 6 reference clock edge select 5 Reserved 4 Reserved PHY Power 3 ...
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Micrel, Inc. Global Registers (Continued) Address Name Register 12 (0x0C): Global Control 10 7 Reserved Satus of device with RMII interface at clock mode or normal mode, default is clock mode with 25MHz 6 Crystal clock from pins X1/X2 (used ...
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Micrel, Inc. Global Registers (Continued) Address Name 5 PLL Power Down 4 – 3 Power Management Mode 2-0 Reserved Register 15 (0x0F): Power Down Management Control 2 7 – 0 Go_sleep_time[7:0] March 2012 Description Pll power down enable ...
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Micrel, Inc. Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. ...
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Micrel, Inc. Port Registers (Continued) Address Name 0 Two Queues Split Enable Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Register 65 (0x41): Port 4 Control 1 ...
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Micrel, Inc. Port Registers (Continued) Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Register 66 (0x42): Port 4 Control 2 Register 82 (0x52): Port 5 Control 2 ...
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Micrel, Inc. Port Registers (Continued) Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Register 67 (0x43): Port 4 Control 3 Register 83 (0x53): Port 5 Control 3 ...
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Micrel, Inc. Port Registers (Continued) Register 25 (0x19): Port 1 Status 0 Register 41 (0x29): Port 2 Status 0 Register 57 (0x39): Port 3 Status 0 Register 73 (0x49): Port 4 Status 0 Register 89 (0x59): Port 5 Status 0 ...
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Micrel, Inc. Port Registers (Continued) Register 27 (0x1B): Reserved Register 43 (0x2B): Reserved Register 59 (0x3B): Reserved Register 75 (0x4B): Reserved Register 91 (0x5B): Reserved Address Name 7-0 Reserved Register 28 (0x1C): Port 1 Control 5 Register 44 (0x2C): Port ...
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Micrel, Inc. Port Registers (Continued) Address Name Advertised Flow Control 4 Capability Advertised 100BT Full- 3 Duplex Capability Advertised 100BT Half- 2 Duplex Capability Advertised 10BT Full- 1 Duplex Capability Advertised 10BT Half- 0 Duplex Capability Register 29 (0x1D): Port ...
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Micrel, Inc. Port Registers (Continued) Register 30 (0x1E): Port 1 Status 1 Register 46 (0x2E): Port 2 Status 1 Register 62 (0x3E): Port 3 Status 1 Register 78 (0x4E): Port 4 Status 1 Register 94 (0x5E): Port 5 Status 1 ...
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Micrel, Inc. Port Registers (Continued) Address Name Port Operation Mode 2-0 Indication Note: Port Control 12 and 13, 14 and Port Status 1,2 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition. Advanced Control Registers ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name 1-0 Indirect Address High Address Name Register 111 (0x6F): Indirect Access Control 1 7-0 Indirect Address Low Note: Write to Register 111 will actually trigger a command. Read or write access will ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name Register 124 (0x7C): Interrupt Status Register 7 – 5 Reserved 4 Port 5 Interrupt Status 3 Port 4 Interrupt Status 2 Port 3 Interrupt Status 1 Port 2 Interrupt Status 0 Port ...
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Micrel, Inc. Advanced Control Registers (Continued) The registers 128, 129 can be used to map from 802.1p priority field 0-7 to switch’s four priority queues 0-3, 0x3 is highest priority queues as priority 3, 0x0 is lowest priority queues as ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name 0 Reserved Register 131 (0x83): Global Control 15 7 Reserved 6 Reserved Unknown unicast packet 5 forward Unknown unicast packet 4 – 0 forward port map Register 132 (0x84): Global Control 16 ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name Register 134 (0x86): Global Control 18 7 Reserved 6 Self Address Filter Enable Unknown IP multicast packet 5 forward Unknown IP multicast packet 4 – 0 forward port map Register 135 (0x87): ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name 1 – 0 DSCP[1:0] Register 145 (0x91): TOS Priority Control Register 1 7 – 6 DSCP[15:14] 5 – 4 DSCP[13:12] 3 – 2 DSCP[11:10] 1 – 0 DSCP[9:8] Register 146 (0x92): TOS ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name Register 151 (0x97): TOS Priority Control Register 7 7 – 6 DSCP[63:62] 5 – 4 DSCP[61:60] 3 – 2 DSCP[59:58] 1 – 0 DSCP[57:56] Register 152 (0x98): TOS Priority Control Register 8 ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name Register 157 (0x9D): TOS Priority Control Register 13 7 – 6 DSCP[111:110] 5 – 4 DSCP[109:108] 3 – 2 DSCP[107:106] 1 – 0 DSCP[105:104] Register 158 (0x9E): TOS Priority Control Register 14 ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name Insert Source Port PVID for Untagged Packet Destination to Second Lowest Egress Port 1 Note: Enabled by the register 135 bit 2 Insert Source Port PVID for Untagged Packet Destination to Lowest ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name Register 178 (0xB2): Port 1 Control 10 Register 194 (0xC2): Port 2 Control 10 Register 210 (0xD2): Port 3 Control 10 Register 226 (0xE2): Port 4 Control 10 Register 242 (0xF2): Port ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name Register 181 (0xB5): Port 1 Control 13 Register 197 (0xC5): Port 2 Control 13 Register 213 (0xD5): Port 3 Control 13 Register 229 (0xE5): Port 4 Control 13 Register 245 (0xF5): Port ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1 Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1 Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1 Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1 Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control ...
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Micrel, Inc. Advanced Control Registers (Continued) Address Name Register 190 (0xBE) : Port 1 Queue 3 Egress Limit Control 4 Register 206 (0xCE) : Port 2 Queue 3 Egress Limit Control 4 Register 222 (0xDE) : Port 3 Queue 3 ...
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Micrel, Inc. Data Rate Selection Table in 100BT Rate for 100BT mode 1 Mbps <= rate <= 99 Mbps rate = 100 Mbps Less than 1Mbps see as below 64 Kbps 128 Kbps 192 Kbps 256 Kbps 320 Kbps 384 ...
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Micrel, Inc. Address Name Register 191(0xBF): Testing Register Reserved Register 207(0xCF): Reserved Control Register Reserved Register 223(0xDF): Test Register Reserved Register 239(0xEF): Test Register Reserved Register ...
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Micrel, Inc. Static MAC Address Table KSZ8895MQ/RQ/FMQ has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to make a packet forwarding decision. When an SA look-up is requested, only the ...
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Micrel, Inc. Examples: (1) Static Address Table Read (read the 2 Write to Register 110 with 0x10 (read static table selected) Write to Register 111 with 0x1 (trigger the read operation) Then Read Register 113 (63-56) Read Register 114 (55-48) ...
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Micrel, Inc. VLAN Table The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit 7 = 1), this table is used to retrieve VLAN information that is associated with the ingress packet. ...
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Micrel, Inc. Write to Register 110 (0x6E) with 0x14 (read VLAN table selected) Write to Register 111 (0x6F) with 0x0 (trigger the read operation for VID = entries) Then read the indirect data registers bits[38-26] for ...
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Micrel, Inc. Dynamic MAC Address Table This table is read only. The contents are maintained by the KSZ8895MQ/RQ/FMQ only. Address Name Format of Dynamic MAC Address Table (1K entries) 71 MAC Empty 70- Valid Entries 60-59 Time Stamp ...
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Micrel, Inc. MIB (Management Information Base) Counters The MIB counters are provided on per port basis. These counters are read using indirect memory access as below: For Port 1 Offset Counter Name Description 0x0 RxLoPriorityByte Rx lo-priority (default) octet count ...
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Micrel, Inc. For port 2, the base is 0x20, same offset definition (0x20-0x3f) For port 3, the base is 0x40, same offset definition (0x40-0x5f) For port 4, the base is 0x60, same offset definition (0x60-0x7f) For port 5, the base ...
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Micrel, Inc. The KSZ8895MQ/RQ/FMQ provides a total of 34 MIB counters per port. These counters are used to monitor the port detail activity for network management and maintenance. These MIB counters are read using indirect memory access, per the following ...
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Micrel, Inc. MIIM Registers All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms are used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for Port ...
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Micrel, Inc. MIIM Registers (Continued) Address Name Register 1h: MII Status 15 T4 Capable 14 100 Full Capable 13 100 Half Capable 12 10 Full Capable 11 10 Half Capable 10-7 Reserved 6 Preamble Suppressed 5 AN Complete 4 far ...
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Micrel, Inc. MIIM Registers (Continued) Address Name Register 5h: Link Partner Ability 15 Next Page 14 LP ACK 13 Remote fault 12-11 Reserved 10 Pause 9 Reserved Address Name 8 Adv 100 Full 7 Adv 100 Half 6 Adv 10 ...
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Micrel, Inc. MIIM Registers (Continued) Address Name 1 Remote Loopback 0 Reserved March 2012 Description 1 = Perform Remote loopback, loop back path as follows: Port 1 (PHY ID address 0x1 reg. 1f, bit 1 = ‘1’) Start: RXP1/RXM1 (port ...
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Micrel, Inc. Absolute Maximum Ratings Supply Voltage ( .......................–0.5V to +2.4V DDAR DDAP DDC ( .................................–0.5V to +4.0V DDAT DDIO Input Voltage ........................................–0.5V to +4.0V Output Voltage .....................................–0.5V to +4.0V Lead Temperature ...
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Micrel, Inc. Symbol Parameter TTL Outputs V Output High Voltage (VDDIO=3.3/2.5/1.8V Output Low Voltage (VDDIO=3.3/2.5/1.8V Output Tri-State Leakage OZ 100BASE-TX Transmit (measured differentially after 1:1 transformer) V Peak Differential Output Voltage O V Output Voltage Imbalance ...
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Micrel, Inc. Timing Diagrams EEPROM Timing Figure 13. EEPROM Interface Input Receive Timing Diagram Figure 14. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter t Clock Cycle CYC1 t Set-Up Time S1 t Hold Time H1 t Output Valid OV1 ...
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Micrel, Inc. SNI Timing Symbol Parameter t Clock Cycle CYC2 t Set-Up Time S2 t Hold Time H2 t Output Valid O2 March 2012 Figure 15. SNI Input Timing Figure 16. SNI Output Timing Table 24. SNI Timing Parameters 104 ...
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Micrel, Inc. MII Timing Figure 17. MAC Mode MII Timing – Data Received from MII Figure 18. MAC Mode MII Timing – Data Transmitted from MII Symbol March 2012 10Base-T/100Base-TX Parameter Min Typ t Clock Cycle 400/40 CYC3 t Set-Up ...
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Micrel, Inc. Figure 19. PHY Mode MII Timing – Data Received from MII Figure 20. PHY Mode MII Timing – Data Transmitted from MII Symbol March 2012 10BaseT/100BaseT Parameter Min t Clock Cycle 400/40 CYC4 t Set-Up Time 10 S4 ...
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Micrel, Inc. RMII Timing Timing Parameter t cyc March 2012 Figure 21. RMII Timing – Data Received from RMII Figure 22. RMII Timing – Data Transmitted to RMII Description Min Clock cycle Setup time ...
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Micrel, Inc. SPI Timing Symbol Parameter f Clock Frequency C t SPIS_N Inactive Hold Time CHSL t SPIS_N Active Set-Up Time SLCH t SPIS_N Active Hold Time CHSH t SPIS_N Inactive Set-Up Time SHCH t SPIS_N Deselect Time SHSL t ...
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Micrel, Inc. Symbol Parameter f Clock Frequency C t SPIQ Hold Time CLQX t Clock Low to SPIQ Valid CLQV t Clock High Time CH t Clock Low Time CL t SPIQ Rise Time QLQH t SPIQ fall Time QHQL ...
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Micrel, Inc. Auto-Negotiation Timing Symbols Parameters t FLP burst to FLP burst BTB t FLP burst width FLPW t Clock/Data pulse width PW t Clock pulse to Data pulse CTD t Clock pulse to Clock pulse CTC Number of Clock/Data ...
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Micrel, Inc. MDC/MDIO Timing Timing Parameter Description t MDC period P t MDIO (PHY input) setup to rising edge of MDC 1MD1 t MDIO (PHY input) hold from rising edge of MDC MD2 t MDIO (PHY output) delay from rising ...
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Micrel, Inc. Reset Timing Symbol Parameter t Stable Supply Voltages to Reset High SR t Configuration Set-Up Time CS t Configuration Hold Time CH t Reset to Strap-In Pin Output RC tvr 3.3V rise time March 2012 Figure 27. Reset ...
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Micrel, Inc. Reset Circuit Diagram Micrel recommends the following discrete reset circuit as shown in Figure 22 when powering up the KS8895MQ device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we ...
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Micrel, Inc. Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common- mode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps ...
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Micrel, Inc. Package Information March 2012 128-Pin PQFP 115 KSZ8895MQ/RQ/FMQ M9999-032612-1.5 ...
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Micrel, Inc. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this ...