KSZ8895MQ_12 MICREL [Micrel Semiconductor], KSZ8895MQ_12 Datasheet - Page 47

• Manufacturer Part Number: KSZ8895MQ_12
• Description: Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Egress Rate Limit
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic.
Interframe gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each
output priority queue is limited by the egress rate specified by the data rate selection table followed the egress rate
limit control registers.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in
the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow
control will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping
at the ingress end, and may be therefore slightly less than the specified egress rate. The egress rate limiting
supports the port-based, 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0-3 selection by
bits[4-3] of the port register control 0. The 802.1p and DiffServ-based priority can be mapped to priority 0-3 by default
of the register 128 and 129. In the egress rate limit, set register 135 global control 19 bit 3 for queue-based rate limit
to be enabled if using two-queue or four-queue mode. All related ingress ports and egress port should be split to two-
queue or four-queue mode by the port registers control 9 and control 0. The four-queue mode will use Q0-Q3 for
priority 0-3 by bit[6-0] of the port register egress limit control 1-4. The two-queue mode will use Q0-Q1 for priority 0-
1by bit[6-0] of the port register egress limit control 1-2. The priority levels in the packets of the 802.1p and DiffServ
can be programmed to priority 0-3 by the register 128 and 129 for a re-mapping.
When the egress rate is limited, just use one queue per port for the egress port rate limit. The priority packets will be
based upon the data rate selection table (see Tables 13 and 14). If the egress rate limit uses more than one queue
per port for the egress port rate limit, then the highest priority packets will be based upon the data rate selection table
for the rate limit exact number. Other lower priority packet rates will be limited based upon 8:4:2:1 (default) priority
ratio, which is based on the highest priority rate. The transmit queue priority ratio is programmable.
To reduce congestion, it is good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Transmit Queue Ratio Programming
In transmit queues 0-3 of the egress port, the default priority ratio is 8:4:2:1. The priority ratio can be programmed by
the port registers control 10, 11, 12 and 13. When the transmit rate exceeds the ratio limit in the transmit queue, the
transmit rate will be limited by the transmit queue 0-3 ratio of the port register control 10, 11, 12 and 13. The highest
priority queue will not be limited. Other lower priority queues will be limited based on the transmit queue ratio.
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast
Enable Self-address filtering, the unknown unicast packet filtering and forwarding by the Register 131 Global Control
15. Enable Unknown multicast packet filtering and forwarding by the Register 132 Global Control 16.
Enable Unknown VID packet filtering and forwarding by the Register 133 Global Control 17.
Enable Unknown IP multicast packet filtering and forwarding by the Register 134 Global Control 18.
This function is very useful in preventing packets that could degrade the quality of the port in applications such as
voice over Internet Protocol (VoIP) and the daisy chain connection.
Configuration Interface
2
I
C Master Serial Bus Configuration
If a 2-wire EEPROM exists, then the KSZ8895MQ/RQ/FMQ can perform more advanced features like broadcast
storm protection and rate control. The EEPROM should have the entire valid configuration data from Register 0 to
Register 255 defined in the “Memory Map,” except the chipID = 0 in the register1 and the status registers. After reset,
the KSZ8895MQ/RQ/FMQ will start to read all 255 registers sequentially from the EEPROM. The configuration
access time (t
) is less than 30ms, as shown in Figure 8.
prgm
47
March 2012
M9999-032612-1.5