KSZ8895MQ_12 MICREL [Micrel Semiconductor], KSZ8895MQ_12 Datasheet - Page 24

• Manufacturer Part Number: KSZ8895MQ_12
• Description: Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Introduction
The KSZ8895MQ/RQ/FMQ contains five 10/100 physical layer transceivers and five media access control (MAC)
units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode is as a five-port
integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this
mode, access to the fifth MAC is provided through a media independent interface (MII/RMII). This is useful for
implementing an integrated broadband router. The third mode uses the dual MII/RMII feature to recover the use of
the fifth PHY. This allows the additional broadband gateway configuration, where the fifth PHY may be accessed
through the P5-MII/RMII port.
The KSZ8895MQ/RQ/FMQ has the flexibility to reside in a managed or unmanaged design. In a managed design, a
host processor has complete control of the KSZ8895MQ/RQ/FMQ via the SPI bus, or the MDC/MDIO interface. An
unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time.
On the media side, the KSZ8895MQ/RQ/FMQ supports IEEE 802.3 10BASE-T, 100BASE-TX on all copper ports
with Auto MDI/MDIX. The KSZ8895FMQ supports 100BASE-FX on port 3 and port 4. The KSZ8895MQ/RQ/FMQ can
be used as a fully managed five-port switch or hooked up to a microprocessor by its SW-MII/RMII interfaces for any
application solutions.
Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the
design more efficient and allows for reduced power consumption and smaller chip die size.
Major enhancements from the KS8895MA/FQ to the KSZ8895MQ/FMQ include more host interface options, a dual-
switch MAC5 MII and PHY5 MII interfaces with other options, RMII from part of the KSZ8895RQ, tag and port-based
VLAN, rapid spanning tree support, IGMP snooping support, port mirroring support, more flexible rate limiting, and
new filtering functionality.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts
the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B
coding followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then
transmitted in MLT3 current output. The output current is set by an external 1% 12.4kΩ resistor for the 1:1
transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding
amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the
100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data
and clock recovery, NRZI-to-NRZ conversion, descrambling, 4B/5B decoding, and serial-to-parallel conversion. The
receiving side starts with the equalization filter to compensate for intersymbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to
adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial
estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes
itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as
temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is
used to compensate for the effect of baseline wander and improve the dynamic range. The differential data
conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by
the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the
MAC.
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March 2012
M9999-032612-1.5