KSZ8895MQ_12 MICREL [Micrel Semiconductor], KSZ8895MQ_12 Datasheet - Page 51

• Manufacturer Part Number: KSZ8895MQ_12
• Description: Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
MII Management Interface (MIIM)
The KSZ8895MQ/RQ/FMQ supports the standard IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control
the states of the KSZ8895MQ/RQ/FMQ. An external device with MDC/MDIO capability is used to read the PHY
status or configure the PHY settings. Further details on the MIIM interface are found in Clause 22.2.4.5 of the IEEE
802.3u Specification.
The MIIM interface consists of the following:
The MIIM Interface can operate up to a maximum clock speed of 10MHz MDC clock.
The following table depicts the MII Management Interface frame format.
The MIIM interface does not have access to all the configuration registers in the KSZ8895MQ/RQ/FMQ. It can only
access the standard MIIM registers. See “MIIM Registers”. The SPI interface and MDC/MDIO SMI mode, on the
other hand, can be used to access all registers with the entire KSZ8895MQ/RQ/FMQ feature set.
Serial Management Interface (SMI)
The SMI is the KSZ8895MQ/RQ/FMQ non-standard MIIM interface that provides access to all KSZ8895MQ/RQ/FMQ
configuration registers. This interface allows an external device with MDC/MDIO interface to completely monitor and
control the states of the KSZ8895MQ/RQ/FMQ.
The SMI interface consists of the following:
The SMI Interface can operate up to a maximum clock speed of 10MHz MDC clock.
The following table depicts the SMI frame format.
March 2012
Read
Write
Read
Write
 A physical connection that incorporates the data line (pin 108 MDIO) and the clock line (pin 107 MDC).
 A specific protocol that operates across the aforementioned physical connection that allows an external
 Access to a set of eight 16-bit registers, consisting of 8 standard MIIM registers [0:5h], 1d and 1f MIIM



controller to communicate with the KSZ8895MQ/RQ/FMQ device.
registers per port.
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8895MQ/RQ/FMQ device.
Access to all KSZ8895MQ/RQ/FMQ configuration registers. Register access includes the Global, Port and
Advanced Control Registers 0-255 (0x00 – 0xFF), and indirect access to the standard MIIM registers [0:5]
and custom MIIM registers [29, 31].
Preamble
32 1’s
32 1’s
Preamble
32 1’s
32 1’s
Start of
Frame
01
01
Start of
Frame
01
01
Table 12. Serial Management Interface (SMI) Frame Format
Table 11. MII Management Interface Frame Format
Read/Write
OP Code
10
01
Read/Write
OP Code
10
01
PHY
Address
Bits[4:0]
RR11R
RR11R
Address
Bits[4:0]
AAAAA
AAAAA
PHY
51
REG
Address
Bits[4:0]
RRRRR
RRRRR
Address
Bits[4:0]
RRRRR
RRRRR
REG
TA
Z0
10
TA
Z0
10
Data
Bits[15:0]
0000_0000_DDDD_DDDD
xxxx_xxxx_DDDD_DDDD
Data Bits[15:0]
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
KSZ8895MQ/RQ/FMQ
M9999-032612-1.5
Idle
Z
Z
Idle
Z
Z