ep610i-15 Altera Corporation, ep610i-15 Datasheet - Page 8
ep610i-15
Manufacturer Part Number
ep610i-15
Description
Epld Family
Manufacturer
Altera Corporation
Datasheet
1.EP610I-15.pdf
(42 pages)
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Classic EPLD Family Data Sheet
Figure 5. Classic Switching Waveforms
752
t
Inputs are driven at 3 V
for a logic high and
0 V for a logic low.
All timing characteristics
are measured at 1.5 V.
R
and t
F
< 3 ns.
Register Output to Logic Array
Global Clock at Register
Clock from Logic Array
Clock from Logic Array
Data from Logic Array
Data from Logic Array
Clock into Logic Array
Data from Logic Array
Logic Array Output
Logic Array Input
Global Clock Pin
Output Pin
Output Pin
Clock Pin
Input Pin
I/O Pin
Input Mode
Global Clock Mode
Array Clock Mode
Output Mode
t
R
t
R
t
IO
t
t
IN
t
SU
IN
t
IN
t
t
CH
ACH
t
OD
t
t
IC
t
H
ICS
t
ASU
t
t
PD1
PD2
= t
= t
t
t
t
LAD
CLR
AH
IN
IO
+ t
+ t
t
t
t
ACL
FD
CL
LAD
IN
+ t
+ t
LAD
OD
t
XZ
+ t
t
High-Impedance
OD
OD
Tri-State
t
F
t
t
F
ZX
Altera Corporation
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