ep610i-15 Altera Corporation, ep610i-15 Datasheet - Page 33

• Manufacturer Part Number: ep610i-15
• Description: Epld Family
• Manufacturer: Altera Corporation

Features
Figure 15. EP1810 Package Pin-Out Diagrams
Altera Corporation
Package outlines not drawn to scale. See
Windows in ceramic packages only.
L
K
J
H
G
F
E
D
C
B
A
1
2
3
68-Pin PGA
4
EP1810
5
Bottom
View
6
7
8
High-performance, 48-macrocell Classic EPLD
–
–
–
Programmable I/O architecture with up to 64 inputs or 48 outputs
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in the following packages (see
–
–
9
10 11
Table 32 on page 785
Combinatorial speeds with t
Counter frequencies of up to 50 MHz
Pipelined data rates of up to 62.5 MHz
68-pin ceramic pin-grid array (PGA)
68-pin plastic J-lead chip carrier (PLCC)
CLK1/INPUT
CLK2/INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VCC
I/O
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
of this data sheet for PGA package pin-out information.
68-Pin PLCC
EP1810
PD
as fast as 20 ns
Figure
EP1810 EPLD
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
15)
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
CLK4/INPUT
VCC
CLK3/INPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
777