ep610i-15 Altera Corporation, ep610i-15 Datasheet - Page 23

• Manufacturer Part Number: ep610i-15
• Description: Epld Family
• Manufacturer: Altera Corporation

Features
Altera Corporation
Figure 11. EP910 Package Pin-Out Diagrams
Package outlines are not drawn to scale. Windows in ceramic packages only.
High-performance, 24-macrocell Classic EPLD
–
–
–
Programmable I/O architecture with up to 36 inputs or 24 outputs
EP910 and EP910I devices are pin-, function-, and programming file-
compatible
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in the following packages (see
–
–
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Combinatorial speeds with t
Counter frequencies of up to 76.9 MHz
Pipelined data rates of up to 125 MHz
44-pin plastic J-lead chip carrier (PLCC)
40-pin ceramic and plastic dual in-line packages (CerDIP and
PDIP)
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
6
5
44-Pin PLCC
4
3
EP910
EP910I
2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
PD
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
as fast as 12 ns
Figure
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
CLK1
GND
EP910 EPLD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
11)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-Pin DIP
EP910
EP910I
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
CLK2
767