ep610i-15 Altera Corporation, ep610i-15 Datasheet - Page 6

• Manufacturer Part Number: ep610i-15
• Description: Epld Family
• Manufacturer: Altera Corporation

Classic EPLD Family Data Sheet
Design Security
Timing Model
750
EP610, EP610I, EP910, and EP910I devices have a global feedback
configuration; either the macrocell output (Q) or the I/O pin input (I/O)
can feed back to the AND array so that it is accessible to all other
macrocells.
EP1810 macrocells can have either of two feedback configurations:
quadrant or dual. Most macrocells in EP1810 devices have a quadrant
feedback configuration; either the macrocell output or I/O pin input can
feed back to other macrocells in the same quadrant. Selected macrocells in
EP1810 devices have a dual feedback configuration: the output of the
macrocell feeds back to other macrocells in the same quadrant, and the
I/O pin input feeds back to all macrocells in the device. If the associated
I/O pin is not used, the macrocell output can optionally feed all
macrocells in the device. In this case, the output of the macrocell passes
through the tri-state buffer and uses the feedback path between the buffer
and the I/O pin.
Classic devices contain a programmable security bit that controls access to
the data programmed into the device. When this bit is programmed, a
proprietary design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security because
data within configuration elements is invisible. The security bit that
controls this function and other program data is reset only when the
device is erased.
Device timing can be analyzed with the MAX+PLUS II software, with a
variety of popular industry-standard EDA simulators and timing
analyzers, or with the timing model shown in
internal delays that allow the user to determine the worst-case timing for
any design. The MAX+PLUS II software provides timing simulation,
point-to-point delay prediction, and detailed timing analysis for system-
level performance evaluation.
Figure 4. Classic Timing Model
Delay
Delay
Input
I/O
t
t
IN
IO
Global Clock
Logic Array
Array Clock
Delay
Delay
Delay
t
t
t
t
LAD
CLR
ICS
IC
Register
Feedback
t
t
Delay
Figure
SU
H
t
FD
4. Devices have fixed
Altera Corporation
Output
Delay
t
t
t
OD
XZ
ZX