ep610i-15 Altera Corporation, ep610i-15 Datasheet - Page 31

• Manufacturer Part Number: ep610i-15
• Description: Epld Family
• Manufacturer: Altera Corporation

Altera Corporation
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
IN
IO
LAD
OD
ZX
XZ
SU
H
IC
ICS
FD
CLR
Table 22. EP910I Internal Timing Parameters
These values are specified in
See
timing parameters.
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
Sample-tested only for an output change of 500 mV.
The f
Measured with the device programmed as a 24-bit counter.
Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both
global and array clocking.
Application Note 78 (Understanding MAX 5000 & Classic Timing)
MAX
Input pad and buffer delay
I/O input pad and buffer delay
Logic array delay
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
Register setup time
Register hold time
Array clock delay
Global clock delay
Feedback delay
Register clear time
values represent the highest frequency for pipelined data.
Parameter
Table 15 on page
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
Condition
770.
Min
EP910I-12
4.0
4.0
in this data book for information on internal
Max
12.0
11.0
2.0
0.0
8.0
2.0
5.0
5.0
4.0
1.0
Classic EPLD Family Data Sheet
Min
EP910I-15
5.0
6.0
Max
12.0
12.0
3.0
0.0
9.0
3.0
6.0
6.0
3.0
1.0
Min
11.0
EP910I-25
5.0
Max
17.0
14.0
20.0
2.0
0.0
6.0
9.0
9.0
6.0
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
775