ep610i-15 Altera Corporation, ep610i-15 Datasheet - Page 12

• Manufacturer Part Number: ep610i-15
• Description: Epld Family
• Manufacturer: Altera Corporation

Classic EPLD Family Data Sheet
General
Description
Figure 8. EP610 Block Diagram
756
Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages.
11
2 (3)
1 (2)
(13)
10
3
4
5
6
7
8
9
INPUT
INPUT
CLK1
(10)
(12)
(4)
(5)
(6)
(7)
(8)
(9)
EP610 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins,
and 2 global clock pins (see
from the global bus, which consists of the true and complement forms of
the dedicated inputs and the true and complement forms of either the
output of the macrocell or the I/O input. The CLK1 signal is a dedicated
global clock input for the registers in macrocells 9 through 16. The CLK2
signal is a dedicated global clock input for registers in macrocells 1
through 8.
Figure 9
devices.
Figure 9. I
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
shows the typical supply current (I
CC
Typical I
Active (mA)
vs. Frequency of EP610 Devices
CC
100
Global
1.0
0.1
10
Bus
1 kHz
Figure
V
T
A
CC
= 25 C
= 5.0 V
10 kHz 100 kHz 1 MHz 10 MHz 80 MHz
8). Each macrocell can access signals
Turbo
Macrocell 4
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
Frequency
Non-Turbo
CC
) versus frequency of EP610
Altera Corporation
(26)
(25)
(24)
(23)
(22)
(21)
(20)
(18)
INPUT
CLK2
INPUT
22
21
20
19
18
17
16
15
(27)
(16)
(17)
23
13
14