ep610i-15 Altera Corporation, ep610i-15 Datasheet - Page 11

• Manufacturer Part Number: ep610i-15
• Description: Epld Family
• Manufacturer: Altera Corporation

Features
Figure 7. EP610 Package Pin-Out Diagrams
Altera Corporation
Package outlines not drawn to scale. Windows in ceramic packages only.
INPUT
INPUT
CLK1
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
24-Pin SOIC
1
2
3
4
5
6
7
8
9
10
11
12
EP610
24
23
22
21
20
19
18
17
16
15
14
13
VCC
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
CLK2
High-performance, 16-macrocell Classic EPLD
–
–
–
Programmable I/O architecture with up to 20 inputs or 16 outputs
and 2 clock pins
EP610 and EP610I devices are pin-, function-, and programming
file-compatible
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in the following packages (see
–
–
–
INPUT
INPUT
CLK1
Combinatorial speeds with t
Counter frequencies of up to 100 MHz
Pipelined data rates of up to 125 MHz
24-pin small-outline integrated circuit (plastic SOIC only)
24-pin ceramic and plastic dual in-line package (CerDIP and
PDIP)
28-pin plastic J-lead chip carrier (PLCC)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
24-Pin DIP
1
2
3
4
5
6
7
8
9
10
11
12
EP610
EP610I
24
23
22
21
20
19
18
17
16
15
14
13
VCC
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
CLK2
PD
NC
I/O
I/O
I/O
I/O
I/O
I/O
as fast as 10 ns
5
6
7
8
9
10
11
12
Figure
4
13
3
28-Pin PLCC
EP610 EPLD
14
2
EP610
EP610
EP610I
7):
15
1
28
16
27
17
18
26
25
24
23
22
21
20
19
I/O
I/O
I/O
I/O
I/O
I/O
NC
755