ep610i-15 Altera Corporation, ep610i-15 Datasheet - Page 41

• Manufacturer Part Number: ep610i-15
• Description: Epld Family
• Manufacturer: Altera Corporation

Altera Corporation
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
Pin-Out
Information
These values are specified in
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
Measured with a device programmed as four 12-bit counters.
Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter
applies for both global and array clocking.
The f
Sample-tested only for an output change of 500 mV.
MAX
values represent the highest frequency for pipelined data.
Table 32
packages.
A10
Pin
Table 32. EP1810 PGA Pin-Outs
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
Table 24 on page
I/O
I/O
I/O
INPUT
CLK4/INPUT
CLK3/INPUT C10
INPUT
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
VCC
INPUT
INPUT
Function
provides pin-out information for EP1810 devices in 68-pin PGA
781.
B10
B11
C11
D10
D11
E10
E11
Pin
C1
C2
D1
D2
B9
E1
E2
F1
F2
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
G10
G11
H10
H11
F10
F11
J10
J11
Pin
G1
G2
H1
H2
K1
K2
K3
J1
J2
Classic EPLD Family Data Sheet
Function
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
K10 I/O
K11 I/O
L10 I/O
Pin
K4
K5
K6
K7
K8
K9
L2
L3
L4
L5
L6
L7
L8
L9
INPUT
INPUT
VCC
INPUT
INPUT
I/O
I/O
I/O
INPUT
CLK1/INPUT
CLK2/INPUT
INPUT
I/O
I/O
Function
785