s71jl064ha0bfw62 Advanced Micro Devices, s71jl064ha0bfw62 Datasheet - Page 72

• Manufacturer Part Number: s71jl064ha0bfw62
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram Cmos 3.0volt-only, Simultaneous Operation Flash Memories And Static Ram/pseudo-static Ram
• Manufacturer: Advanced Micro Devices

Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for
3. When reading write operation status bits, the system must always provide the bank address where the Embedded
72
Standard
Suspend
Erase
limits. Refer to the section on DQ5 for more information.
further details.
Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
Mode
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Erase-Suspend-Program
Erase-Suspend-
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device will accept addi-
tional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each sub-
sequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 12
Read
Status
shows the status of DQ3 relative to the other status bits.
Erase
Suspended Sector
Non-Erase
Suspended Sector
Table 12. Write Operation Status
(Note 2)
DQ7#
DQ7#
Data
DQ7
S29JL064H
0
1
P r e l i m i n a r y
No toggle
Toggle
Toggle
Toggle
Data
DQ6
(Note 1)
Data
DQ5
0
0
0
0
Data
DQ3
N/A
N/A
N/A
1
S71JLxxxHxx_00A1 February 25, 2004
No toggle
(Note 2)
Toggle
Toggle
Data
DQ2
N/A
RY/BY#
0
0
1
1
0