s71jl064ha0bfw62 Advanced Micro Devices, s71jl064ha0bfw62 Datasheet - Page 66

• Manufacturer Part Number: s71jl064ha0bfw62
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram Cmos 3.0volt-only, Simultaneous Operation Flash Memories And Static Ram/pseudo-static Ram
• Manufacturer: Advanced Micro Devices

Notes:
1. See
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth, fifth, and sixth cycle of the autoselect command sequence, all bus cycles
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD.
5. Unless otherwise noted, address bits A21–A11 are don’t cares for unlock and command cycles, unless SA or PA is
6. No unlock or command cycles required when bank is reading array data.
7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in
8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address
9. The device ID must be read across the fourth, fifth, and sixth cycles.
10.The data is 80h for factory locked, 40h for customer locked, and 00h for not factory/customer locked.
11.The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
12.The Unlock Bypass command is required prior to the Unlock Bypass Program command.
13.The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass
14.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend
15.The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.
16.Command is valid when device is ready to read array data or when device is in autoselect mode.
Write Operation Status
66
are write cycles.
required.
Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status
information).
to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15–DQ8 are don’t
care. While reading the autoselect addresses, the bank address must be the same until a reset command is given.
See the
mode.
mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address.
Table 1
DQ7: Data# Polling
"Autoselect Command
for description of bus operations.
The device provides several bits to determine the status of a program or erase
operation: DQ2, DQ3, DQ5, DQ6, and DQ7.
tions describe the function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress.
The device also provides a hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in progress or has been
completed.
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether a bank is in
Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse
in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then that bank returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide
Sequence" section section for more information.
S29JL064H
P r e l i m i n a r y
Table 12
and the following subsec-
S71JLxxxHxx_00A1 February 25, 2004