s71jl064ha0bfw62 Advanced Micro Devices, s71jl064ha0bfw62 Datasheet - Page 108
s71jl064ha0bfw62
Manufacturer Part Number
s71jl064ha0bfw62
Description
Stacked Multi-chip Product Mcp Flash Memory And Psram Cmos 3.0volt-only, Simultaneous Operation Flash Memories And Static Ram/pseudo-static Ram
Manufacturer
Advanced Micro Devices
Datasheet
1.S71JL064HA0BFW62.pdf
(141 pages)
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16 Mb pSRAM (supplier 4)
16 Megabit (1M x 16) CMOS Pseudo SRAM
Features
Description
Pin Description
96
The S71JL064HA0 Model #62 contains a 16M-bit Pseudo SRAM organized as 1M
words by 16 bits. It is designed with advanced CMOS technology specified RAM
featuring low-power static RAM-compatible function and pin configuration. This
device operates from a single power supply. Advanced circuit technology provides
both high speed and low power. It is automatically placed in low-power mode
when CS1# or both UB# and LB# are asserted high or CS2 is asserted low. There
are three control inputs. CS1# and CS2 are used to select the device, and output
enable (OE#) provides fast memory access. Data byte control pins (LB#,UB#)
provide lower and upper byte access. This device is well suited to various micro-
processor system applications where high speed, low power and battery backup
are required.
A0 – A19
DQ0 – DQ15
CE1#
CE2
OE#
WE#
LB#
UB#
VCC
VSS
Organized as 1M words by 16 bits
Fast Cycle Time : 70 ns
Standby Current : 100 µA
Deep power-down Current : 10 µA (Memory cell data invalid)
Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15)
Compatible with low-power SRAM
Single Power Supply Voltage : 3.0V±0.3V
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16 Mb pSRAM (supplier 4)
Address Inputs
Data Inputs/Outputs
Chip Enable
Deep Power Down
Output Enable
Write Control
Lower Byte Control
Upper Byte Control
Power Supply
Ground
P r e l i m i n a r y
S71JLxxxHxx_00A1 February 25, 2004
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