s71jl064ha0bfw62 Advanced Micro Devices, s71jl064ha0bfw62 Datasheet - Page 44

• Manufacturer Part Number: s71jl064ha0bfw62
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram Cmos 3.0volt-only, Simultaneous Operation Flash Memories And Static Ram/pseudo-static Ram
• Manufacturer: Advanced Micro Devices

44
Simultaneous Read/Write Operations with Zero Latency
Standby Mode
Automatic Sleep Mode
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
is one of two functions provided by the WP#/ACC pin. This function is primarily
intended to allow faster manufacturing throughput at the factory.
If the system asserts V
mentioned Unlock Bypass mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing V
turns the device to normal operation. Note that V
WP#/ACC for operations other than accelerated programming, or device damage
may result. In addition, the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result. See “Write Protect
(WP#)” on page 51. for related information.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ15–DQ0. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Command
This device is capable of reading data from one bank of memory while program-
ming or erasing in the other bank of memory. An erase operation may also be
suspended to read from or program to another location within the same bank (ex-
cept the sector being erased).
initiated for simultaneous operation with zero latency. I
Characteristics" section table represent the current specifications for read-while-
program and read-while-erase, respectively.
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V
V
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (t
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
I
specification.
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
CC3
IH
.) If CE# and RESET# are held at V
in the
"DC
CC
Characteristics" section table represents the standby current
± 0.3 V. (Note that this is a more restricted voltage range than
Sequence" section sections for more information.
HH
on this pin, the device automatically enters the afore-
Figure 21
CE
) for read access when the device is in either
S29JL064H
P r e l i m i n a r y
IH
shows how read and write cycles may be
, but not within V
"Autoselect
HH
HH
from the WP#/ACC pin re-
must not be asserted on
CC6
CC
and I
± 0.3 V, the device
Mode" section and
CC7
in the
S71JLxxxHxx_00A1 February 25, 2004
ACC
"DC
+